CS5451A データシートの表示（PDF） - Cirrus Logic

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CS5451A

Six-Channel Delta-Sigma Analog-to-Digital Converter

Cirrus Logic 

CS5451A

SWITCHING CHARACTERISTICS

Parameter

Symbol Min

Typ

Max

Master Clock Frequency

(Note 10) XIN

3

4.000

5

Master Clock Duty Cycle

-

40

-

60

Rise Times

Any Digital Input (Note 11) trise

Any Digital Output

-

-

1.0

-

50

-

Fall Times

Any Digital Input (Note 11) tfall

Any Digital Output

-

-

1.0

-

50

-

Serial Port Timing

Serial Clock Frequency

(Note 10)

OWRS = “0”

OWRS = “1”

SCLK

SCLK

-

500

-

-

1000

-

Serial Clock

Pulse Width High (Note 10)

t1

Pulse Width Low (Note 10)

t2

SCLK falling to New Data Bit

t3

FSO Falling to SCLK Rising Delay

(Note 10)

t4

FSO Pulse Width

(Note 10)

t5

SE Rising to Output Enabled

t6

SE Falling to Output in Tri-state

t7

-

0.5

-

-

0.5

-

-

-

50

-

0.5

-

-

1

-

-

-

50

-

-

50

Notes: 10. Device parameters are specified with a 4. 000MHz clock, OWRS = 1.

11. Specified using 10% and 90% points on wave-form of interest. Output loaded wi th 50pF.

Unit

MHz

%

µs

ns

µs

ns

kHz

kHz

SCLK

SCLK

ns

SCLK

SCLK

ns

ns

SDO

SCLK

FSO

MSB(V1) MSB(V1) - 1

t

3

t1 t2

t4

t5

SE

t6

LSB(I3)

t6

Figure 1. Serial Port Timing

8

DS635PP1

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