CS43L41-KZ データシートの表示（PDF） - Cirrus Logic

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CS43L41-KZ

Low Power 24-Bit, 96 kHz DAC with Volume Control

Cirrus Logic 

CS43L41

LIST OF FIGURES

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Figure 28.

External Serial Mode Input Timing ................................................................................. 9

Internal Serial Mode Input Timing .................................................................................. 9

Internal Serial Clock Generation .................................................................................... 9

I2C Control Port Timing ................................................................................................ 10

SPI Control Port Timing ............................................................................................... 12

Typical Connection Diagram ........................................................................................ 13

SPI Mode Control Port Formatting ............................................................................... 28

I2C Mode Control Port Formatting ................................................................................ 28

Base-Rate Stopband Rejection .................................................................................... 29

Base-Rate Transition Band .......................................................................................... 29

Base-Rate Transition Band (Detail) ............................................................................. 29

Base-Rate Passband Ripple ........................................................................................ 29

High-Rate Stopband Rejection ..................................................................................... 29

High-Rate Transition Band ........................................................................................... 29

High-Rate Transition Band (Detail) .............................................................................. 30

High-Rate Passband Ripple ......................................................................................... 30

Output Test Load ......................................................................................................... 30

Maximum Loading ........................................................................................................ 30

Power vs. Sample Rate (VA = 5V) ............................................................................... 30

CS43L41 Format 0 (I2S) .............................................................................................. 31

CS43L41 Format 1 (I2S) .............................................................................................. 31

CS43L41 Format 2 ....................................................................................................... 31

CS43L41 Format 3 ....................................................................................................... 32

CS43L41 Format 4 ....................................................................................................... 32

CS43L41 Format 5 ....................................................................................................... 32

CS43L41 Format 6 ....................................................................................................... 33

De-Emphasis Curve ..................................................................................................... 33

ATAPI Block Diagram .................................................................................................. 33

LIST OF TABLES

Table 1. Master Clock Divide Enable ............................................................................................... 16

Table 2. Auto-Mute Enable............................................................................................................... 16

Table 3. Digital Interface Formats .................................................................................................... 17

Table 4. De-emphasis Filter Configurations ..................................................................................... 17

Table 5. Power On/Off Ramp Enable ............................................................................................... 18

Table 6. Power Down Enable ........................................................................................................... 18

Table 7. A=B Volume Control Enable............................................................................................... 19

Table 8. Soft Ramp and Zero Cross Enable..................................................................................... 20

Table 9. ATAPI Decode.................................................................................................................... 20

Table 10. Mute Enable ..................................................................................................................... 21

Table 11. Digital Volume Settings .................................................................................................... 22

Table 12. Common Clock Frequencies ............................................................................................ 24

4

DS473PP1

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