CS43L41-KZ データシートの表示（PDF） - Cirrus Logic

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CS43L41-KZ

Low Power 24-Bit, 96 kHz DAC with Volume Control

Cirrus Logic 

CS43L41

SWITCHING CHARACTERISTICS - CONTROL PORT

(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)

Parameter

Symbol

Min

SPI® Mode

CCLK Clock Frequency

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

fsclk

-

tsrs

500

(Note 12)

tspi

500

tcsh

1.0

tcss

20

tscl

66

tsch

66

tdsu

40

(Note 13)

tdh

15

(Note 14)

tr2

-

(Note 14)

tf2

-

Max

Unit

6

MHz

-

ns

-

ns

-

µs

-

ns

-

ns

-

ns

-

ns

-

ns

100

ns

100

ns

Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

13. Data must be held for sufficient time to bridge the transition time of CCLK.

14. For FSCK < 1 MHz

RST

t srs

CS

t spi t css

t scl t sch

t csh

CCLK

t r2

t f2

CDIN

t dsu t dh

Figure 5. SPI Control Port Timing

DS473PP1

11

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