AMMCL002AWP-150I データシートの表示（PDF） - Advanced Micro Devices

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AMMCL002AWP-150I

2 or 4 Megabyte 3.0 Volt-only Flash Miniature Card

Advanced Micro Devices 

PRELIMINARY

Write Enabled

Write Disabled

Figure 3. Write Protect Switch 21138E-1

(Card Right Side View)

In addition to card-level data protection, AMD Flash

Miniature Cards offer several device-level data protec-

tion features.

Device-Level Data Protection

AMD Flash memory devices offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power tran-

sitions. During power up, each device automatically

resets the internal state machine to the read mode. The

control register architecture allows alteration of the

memory contents only occurs after successful comple-

tion of specific multi-bus cycle command sequences.

AMD Flash memory devices also incorporates the fol-

lowing features to prevent inadvertent write cycles

resulting from VCC power-up and power-down transi-

tions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and power-down, the AMD memory devices in the Min-

iature Card lock out write cycles for VCC < VLKO (see

“DC Characteristics” on page 22 for voltages). When

VCC < VLKO, the command register is disabled, all

internal program/erase circuits are disabled, and the

device resets to the read mode. The memory devices

ignore all writes until VCC > VLKO. The user must

ensure that the control pins are in the correct logical

state when VCC > VLKO to prevent unintentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#,

or WE# will neither initiate a write cycle nor change the

command registers.

Logical Inhibit

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH, or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

Power-Up Write Inhibit

Power-up of the device with CE# = WE# = VIL and OE#

= VIH will not accept commands on the rising edge of

WE#. The internal state machine is automatically reset

to the read mode on power-up.

Read Mode

Two Card Enable (CE#) pins are available on the

memory card. Both CE# pins must be active low for

word-wide read accesses. Only one CE# is required for

byte-wide accesses. The CE# pins select and deter-

mine when to apply power to the high-byte and

low-byte memory devices. The Output Enable (OE#)

controls gating accessed data from the memory device

outputs. Refer to Table 4.

The Miniature Card automatically powers up in the

read/reset state. In this case, a command sequence is

not required to read data. Standard microprocessor

read cycles will retrieve array data. This default state

ensures that no spurious alteration of the memory

content occurs during the power transition. Refer to the

AC Read Characteristics and Waveforms for the spe-

cific timing parameters.

Output Disable

Data outputs from the card are disabled when OE# is

at a logic-high level. Under this condition, outputs are

in the high-impedance state.

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