PVG610 データシートの表示（PDF） - Unspecified

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PVG610

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PVG610

Data Sheet

Figure 49: FDD mode.................................................................................................................................................. 95

Figure 50: TDD............................................................................................................................................................ 96

Figure 51: TDD Frame ................................................................................................................................................ 96

Figure 52: XPIC Master-Slave System Configuration................................................................................................. 96

Figure 53: XPIC Interconnection at One End ............................................................................................................. 97

Figure 54: E1/T1/J1 Connection Diagram.................................................................................................................109

Figure 55: E1 Waveform Template Diagram ............................................................................................................112

Figure 56: E1 Pulse Template Test Circuit ...............................................................................................................112

Figure 57: T1 Waveform Template Diagram.............................................................................................................113

Figure 58: T1 Pulse Template Test Circuit ...............................................................................................................113

Figure 59: Transmit Line Circuit................................................................................................................................113

Figure 60: E1/T1/J1 Connections Diagram – External LIU.......................................................................................116

Figure 61: Transmit Timing Diagram ........................................................................................................................117

Figure 62: Receive Timing Diagram .........................................................................................................................117

Figure 63: MDC/MDIO Timing Diagram....................................................................................................................118

Figure 64: MII interface Lines ...................................................................................................................................119

Figure 65: MII Timing Diagrams................................................................................................................................119

Figure 66: GMII interface Lines.................................................................................................................................121

Figure 67: GMII Timing Diagrams.............................................................................................................................122

Figure 68: STM1 Connection Diagram .....................................................................................................................123

Figure 69: STM-1 Timing Diagram............................................................................................................................124

Figure 70: TOH Interface ..........................................................................................................................................125

Figure 71: TOH Extract Interface-Protocol................................................................................................................125

Figure 72: Section DCC Extract Interface-Protocol ..................................................................................................126

Figure 73: Line DCC Extract Interface-Protocol .......................................................................................................126

Figure 74: TOH Timing Diagrams .............................................................................................................................126

Figure 75: Asynchronous GPI with GPM ..................................................................................................................128

Figure 76: RX_ACM signal protocol..........................................................................................................................129

Figure 77: Asynchronous GPI with External Framer ................................................................................................129

Figure 78: Synchronous GPI with GPM ....................................................................................................................130

Figure 79: External Framer with Synchronous GPI ..................................................................................................131

Figure 80: GPI Rx Timing Diagrams .........................................................................................................................132

Figure 81: GPI Tx Timing Diagram ...........................................................................................................................132

Figure 82: EOW CODEC connections with the PVG610..........................................................................................134

Figure 83: EOW Timing Diagrams ............................................................................................................................135

Figure 84: HOST Normal mode - Write and Read transactions ...............................................................................136

Figure 85: HOST Interleaved Mode Read transaction timing diagram,....................................................................137

Figure 86: Connection of external CPU via Host Interface .......................................................................................137

Figure 87: Host Interface in XPIC Configuration (Direct Mode)................................................................................138

Figure 88: Host Interface in XPIC Configuration (DPRAM Mode) ............................................................................138

Figure 89: Slave Read cycle .....................................................................................................................................139

Figure 90: Slave Write...............................................................................................................................................139

Figure 91: Master Read ............................................................................................................................................140

Figure 92: Master Write.............................................................................................................................................140

Figure 93: SPI Connections ......................................................................................................................................141

Figure 94: SPI Master Timing Diagram.....................................................................................................................142

Figure 95: SPI Slave Timing Diagram.......................................................................................................................143

Figure 96: I2C BUS Timing .......................................................................................................................................144

Figure 97: OMI Timing Diagrams..............................................................................................................................146

Figure 98: HDLC Timing Diagrams...........................................................................................................................147

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PVG610A_DSH_002_I3

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