PVG610 データシートの表示（PDF） - Unspecified

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PVG610

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PVG610

Data Sheet

List of Figures

Figure 1: PVG610A General Architecture................................................................................................................... 12

Figure 2: PVG610A Pin Layout 1-17 (Top View) ........................................................................................................ 14

Figure 3: PVG610A Pin Layout 18-34 (Top View) ...................................................................................................... 15

Figure 4: PVG610X (XPIC) Pin Layout 1-17 (Top View) ............................................................................................ 16

Figure 5: PVG610X (XPIC) Pin Layout 18-34 (Top View) .......................................................................................... 17

Figure 6: PVG610A Block Diagram ............................................................................................................................ 45

Figure 7: E1/T1 Port Connection ................................................................................................................................ 46

Figure 8: Rx E1/T1/J1 LIU/Framer Block .................................................................................................................... 47

Figure 9: Tx E1/T1/J1 LIU/Framer Block .................................................................................................................... 48

Figure 10: E1 Frame Format....................................................................................................................................... 49

Figure 11: T1 Frame format ........................................................................................................................................ 50

Figure 12: Ethernet PHY Connection.......................................................................................................................... 52

Figure 13: Ethernet Block Diagram............................................................................................................................. 53

Figure 14: Types of Ethernet Frames ......................................................................................................................... 54

Figure 15: STM-1/OC-3 Connection to PVG610 ........................................................................................................ 56

Figure 16: STM-1/OC-3 Rx Framer Block Diagram.................................................................................................... 57

Figure 17: STM-1/OC-3 Tx Framer Block Diagram .................................................................................................... 58

Figure 18: STM1/OC-3 Frame Format........................................................................................................................ 59

Figure 19: External Mode - GPI connecting directly to the Modem ............................................................................ 61

Figure 20: Internal mode, GPI Port connecting to the GPM ....................................................................................... 61

Figure 21: TX Symbol Clock Locking on External Source .......................................................................................... 62

Figure 22: Synchronous GPI – RX Clock Reconstruction .......................................................................................... 63

Figure 23: GPM Functioning Diagram ........................................................................................................................ 64

Figure 24: Operating in a protection mode ................................................................................................................. 66

Figure 25: PVG610A supporting air modem in ODU .................................................................................................. 69

Figure 26: Cable Interface Block................................................................................................................................. 70

Figure 27: Modem and AFE Block Diagram ............................................................................................................... 71

Figure 28: LDPC Non-Multi Level Coding................................................................................................................... 72

Figure 29: LDPC Multi-Level Encoding....................................................................................................................... 72

Figure 30: Convolutional PTCM Block Diagram ......................................................................................................... 74

Figure 31: Modulator Block Diagram .......................................................................................................................... 75

Figure 32: Pre-emphasis Filter.................................................................................................................................... 76

Figure 33: Demodulator Block Diagram...................................................................................................................... 79

Figure 34: Digital Tuner Block..................................................................................................................................... 80

Figure 35: Symbol Synchronization Block Diagram.................................................................................................... 81

Figure 36: Equalizer Structure .................................................................................................................................... 82

Figure 37: Decoder Block Diagram............................................................................................................................. 83

Figure 38: De-interleaver Block Diagram.................................................................................................................... 84

Figure 39: Reed Solomon Block Diagram................................................................................................................... 85

Figure 40: Variable Nodes .......................................................................................................................................... 86

Figure 41: LDPC Non-Multi-Level Decoding............................................................................................................... 87

Figure 42: LDPC Multi-level Decoding........................................................................................................................ 87

Figure 43: CPU Core Architecture .............................................................................................................................. 88

Figure 44: Channel Capacity Variation ....................................................................................................................... 90

Figure 45: Radial MSE indicator ................................................................................................................................. 92

Figure 46: Basic Airframe Configuration ..................................................................................................................... 94

Figure 47: Full Airframe Configuration ........................................................................................................................ 94

Figure 48: PVG310 Compatible Frame....................................................................................................................... 95

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PVG610A_DSH_002_I3

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