MM1495 データシートの表示（PDF） - Unspecified

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MM1495

I2C BUS Control 5-Input 2-Output AV Switch

Unspecified 

MITSUMI

I2C BUS

I2C BUS Control 5-Input 2-Output AV Switch MM1495X

SDA

SCL

S 12345678A12

8A P

S:Start Condition

P:Stop Condition

A:Acknowledge

I2C BUS is inter bus system controled by 2 lines (SDA, SCL).

Data are transmitted and received in the units of byte and Acknowledge.

It is transmitted by MSB first from the Start conditions.

[Control registers]

Control registers are data sent from the master for determining the switch conditions.

The data format is set as shown in the following figure.

Slave address

R/W

DATA1

S

A

A

1 0 0 1 0 0 0/1 0 b07 b06 b05 b04 b03 b02 b01 b00

Address byte

DATA2

DATA3

A

AP

b17 b16 b15 b14 b13 b12 b11 b10 b27 b26 b25 b24 b23 b22 b21 b20

Out of the Address byte, first 7bit are assigned to the slave address, while the residual 1bit is assigned to the

R/W bit.

Set the R/W bit to 0 when data are used control registers.

As MM1495 slave address, either 90H or 92H can be selected according to the ADR

terminal conditions. When ADR terminal is L, 90H is selected.

The following figure indicates the control contents of control registers and switches.

Each bit of control registers is reset to 0, when power-on.

No.

DATA1

DATA2

DATA3

DATA condition

b07

b06

b05

b04

b03

Y/C select

Mute

Y, CIN1/2 Y, COUT LOUT1 ROUT1 VOUT1

b17

b16

b15

b14

b13

Mute

LOUTTV ROUTTV LOUT2 ROUT2 VOUT2

b27

b26

b25

b24

b23

Output port select

O5

O4

O3

O2

O1

b02

b01

b00

Main V select

b12

b11

b10

Sub V select

b22

b21

b20

Sync sepa select

MM1495 consists of one address byte and three control data bytes (4bytes in total).

All data over the limited length (5th and subsequent bytes) are fully neglected.

For details of the control contents of switches, refer to the separate table.

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