BJ8P153 データシートの表示（PDF） - Unspecified

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BJ8P153

(BJ8P153 / BJ8P508) 8-BIT MICRO-CONTROLLER / OTP ROM

Unspecified 

4. FUNCTION DESCRIPTION

OSCO

OSCI

/RESET

Oscillator/Timing

Control

WDT timer TCC /INT

Prescaler

ROM

BJ8P508/153

OTP ROM

R2

Stack

Built-in

OSC

RAM

Interrupt

Controller

R4

R1(TCC)

Instruction

Register

Instruction

Decoder

ALU

R3

ACC

DATA & CONTROL BUS

P60

P61

IOC6

R6

I/O

PORT 6

P62/TCC

P63//REST

P64/OSCO

P65/OSCI

IOC5

R6

I/O

PORT 5

P50

P51

P52

P53

P66

P67

Fig. 2 Functional block diagram

4.1 Operational Registers

1. R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer.

Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register

(R4).

2. R1 (Time Clock /Counter)

• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or

by the instruction cycle clock.

• Writable and readable as any other registers.

• Defined by resetting PAB (CONT-3).

• The prescaler is assigned to TCC if the PAB bit (CONT-3) is reset.

• The contents of the prescaler counter is cleared only when a value is written to TCC register.

This specification is subject to change without prior notice.

8

6.17.2007 (V2.0)

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