AP1627 データシートの表示（PDF） - Unspecified

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AP1627

Software module of M3L-bus by using HS-SSC for C16x microcontroller family.

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Software module of M3L-bus by using

HS-SSC for C16X uC family

2.2

Timing Diagram

The clock frequency of SCL is in the range of 0 up to 1.0MHz. The clock on the M3L-bus

has a minimum LOW and HIGH period of 400ns.

Occasionally, the MegaText/slave device may slow down the transmission by holding the

clock line low after receiving a byte of data from microcontroller. This phenomenon is

defined as a WAIT condition. Therefore, microcontroller/master needs to switch the SCL

output to high impedance and read the SCL line before transmitting another byte of data

to the slave device.

Figure #3 shows the data transfer timing requirements in detail. The description of the

abbreviations used is shown in the Table #1. The minimum timing requirements are

needed to be fulfilled in order for M3L-bus to operate properly.

I2CEN

tIS

tH IG H

tIM

SCL

tLOW

tDSL

tDSL

SDA

tDHH

tDO

SCL

tDWAIT

WAIT

Figure 3:

M3L-bus timing diagram

tRWAIT

Wait Condition

Semiconductor Group

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AP1627 1.97

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