MSM7712 データシートの表示（PDF） - Oki Electric Industry
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MSM7712 Datasheet PDF : 20 Pages
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–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MSM7712 s
PCMCIA Interface (Continued)
MSM7712GS-K
HIOWRN
HCE1N
HCE2N
HREG
HWAITN
HIOIS16N
HPACKN
HRST
HIREQN
Pin Type
Input
Bidirectional
Bidirectional
Input
Output
Output
Output
Input
Output
PCMCIA
IOWRN
CE1N
CE2N
Reg
WAITN
IOIS16N
PACKN
RST
IREQN
Host Interface Signal Descriptions
Pin Name
HA[8:0]
Direction
Input
HD[15:0]
Bidirectional
HOEN, HWEN,
HIORDN,HIOWRN,
HCE1N, HCE2N,
HREG
Input
HPACKN,
HIOIS16N
Output
HRST
Input
HIREQN
HWAITN
Output
Input
Description
An attribute address range of 512 even bytes accesses is supported. An I/O space of 4 words is used (i.e.
HA[2:0] is used and HA[8:0] is not used).
Attribute memory is standardized to even byte accesses only. Input/Output memory is defined as word ac-
cesses only (to maximize packet transfer rates).
These signals provide the chip selects, read strobes, write strobes as defined in the PCMCIA standard
These signals provide the chip selects, read strobes, write strobes as defined in the PCMCIA standard
The card reset is provided by HRST. HRST must be asserted for a period of time from power up to allow the
oscillator to settle. The MSM7712 is set to a default state while HRST is asserted and SCK is available. From
HRST being deasserted the MSM7712 must download the CIS table from the E2PROM to SRAM before the
reset procedure is considered complete.
HIREQN operates as the RDY/BSY line until the card is configured and hence remains low until the reset pro-
cess is complete (as defined in the PCMCIA standard). Once reset is complete, HIREQN functions as a level-
sensitive interrupt to the host.
Wait states are potentially required when the host accesses the shared memory (to transfer packet data). In-
ternal registers require no wait states.
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