STSR3 データシートの表示（PDF） - STMicroelectronics

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STSR3

SYNCHRONOUS RECTIFIERS SMART DRIVER FOR FLYBACK

STMicroelectronics 

STSR3

PIN DESCRIPTION

Pin N°

1

2

Symbol

NC

VCC

3

SETANT

4

CK

5

INHIBIT

6

SGLGND

7

OUTGATE

8

PWRGND

Name and Function

No internally connected

The supply voltage range from 4.0V to 5.5V allows applications with logic gate

threshold mosfets. UVLO feature guarantees proper start-up while it avoids

undesirable driving during eventual dropping of the supply voltage.

The voltage on this pin sets the anticipation (tANT) in turning off the OUTGATE It is

possible to choose among three different anticipation times by discrete

partitioning of the supply voltage.

This input provides synchronization for IC’s operations, being the transitions

between the two output conditions based on a positive threshold, equal for the

two slopes. A smart internal control logic mechanism using a 15MHz internal

oscillator generates proper anticipation timing at the turn-off of each output. This

feature allows safe turn-off of Synchronous Rectifier avoiding any eventual

shoot-through situation on secondary side at both transitions. Smart clock

revelation mechanism makes these operations independent by false triggering

pulses generated in light load conditions. Absolute maximum voltage rating of the

pin can be exceeded limiting the current flowing into the pin to 10mA max.

This input enables OUTGATE to work when its voltage is lower than the negative

threshold voltage (VINHIBIT<VH). If VINHIBIT>VH the OUTGATE will be high for a

minimum conduction time (tON(GATE)). In typical flyback converter application, it is

possible to turn off the synchronous MOSFET when the current through it tends to

reverse, allowing discontinuous conduction mode and providing protection to the

converter from eventual sinking current from the load.Absolute maximum voltage

rating of the pin can be exceeded limiting the current flowing into the pin to 10mA

max.

Reference for all the control logic signals. This pin is completely separated from

the PWRGND to prevent eventual disturbances to affect the control logic.

Gate Drive signal for synchronous MOSFET. Anticipation [tANT] in turning off

OUTGATE is provided during the transition in which the clock input goes to high

level.

Reference for power signals, this pin carries the full peak currents for the two

outputs.

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