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STV1602A データシートの表示(PDF) - STMicroelectronics

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STV1602A
ST-Microelectronics
STMicroelectronics ST-Microelectronics
STV1602A Datasheet PDF : 22 Pages
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STV1602A
on the printed circuit board. Encircling those two
nodes by a ground guarding is an efficient method
to prevent errors caused by an ”antenna effect”.
Through FV (Pin 35) one can adjust the free run-
ning frequency; when the FV Voltage is equal to
VEE, the free running frequency is the lowest; the
voltage adjustment can be performed by using a
Figure 16 : Serial Data Input and PLL
variable resistor connected between FV and VEE.
RSE (Pin 22) selects the VCO frequency range;
High : 140 to 270MHz, Low : 100 to 145MHz.
When TN1 (Pin 6) is set High, input signals are
disabled and the VCO free runs. The capacitor
connected between TN1 and GND avoids mislock-
ing problem when the power supply is switched on.
From
equalizer
A
Descrambler
NZRI to NRZ
conversion
F
DC
E
D
DL
DL
Phase
Comparator
C
B
VCO
SX
SY
RSE
DIX DIN ADS
TN1
Data detection
Serial data edges are detected and go through low
pass filter. The processed signal is available at
DPR (Pin 35).DPR goes High when an input signal
is detected, otherwise it stays Low.
The driving capability of this pin is weak. It is
recommended to load it with a high impedance
CMOS or equivalent.
5. NRZI To NRZ conversion, descrambler
Serial data delivered by the identifier is available in
differential mode, SX (Pin 4) and SY (Pin 3). At the
same time, to recover the original data, NRZI to
NRZ conversion and descrambling are performed.
Figure 17 : NRZI to NRZ conversion
Serial
Signal
Data
PLL
(NRZI)
D
Clock
Data (NRZ)
ESO ESI FV
Figure 18 : x9 + x4 + 1 Descrambler
In
D1 D2 D3 D4 D5
D6 D7 D8 D9
Out
Figure 19 : Actual x9 + x4 + 1 Descrambler
In D1
D2 D3 D4 D5
D6 D7 D8 D9
D10
Out
6. Serial to parallel conversion
After descrambling, serial data is sent to a 30-bit
register to detect the sync word (TRS). When the
sequence 111111111100000000000000000000is
detected, sync word detection signal is output, the
counter which divides the clock frequency by 10 is
initialized and data is converted to parallel (10-bit
word) to be output.
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