QL80FC データシートの表示（PDF） - QuickLogic Corporation
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QL80FC Datasheet PDF : 21 Pages
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QL80FC - QuickFCTM
User Programmable
Logic
RxRst
RxLOSync
RxLOSIdx[3:0]
RxRawEn
RxData[31:0]
RxRData[39:32]
RxCrcEn
RxIFIdleEn
RxCrcOK
RxCrcRdy
RxSgpBus[14:0]
RxKChar
R xIn vW ord
RxClk63
RxClk125_out
Embedded Fibre Channel ENDEC
Async_rst
From transmit data path
RxClk63 Sync
Reset Circuit
TenbMode
Loss Of Sync
State Machine
8b/10b Decoder
RxIn[19:0]
(only [9:0] used
in 10b mode)
RxComDet
CRC Checking
(SOF, IDLE, EOF . . . )
Ordered Set
Recognition
/2
From transmit
data path
Clk_rst
RxClk125_in
FIGURE 3. .Customizable ENDEC Chip Functional Block Diagram - Receive Data Path
Receive Data Path
RECEIVE DATA PATH
Receive Data Path
The receive data path receives encoded data from an
on-board SERDES, decodes it and passes the result-
ing data to the customizable section of the chip. A
functional block diagram of the receive data path is
shown in Figure 3.
The RxClk125 signal latches 20 bits (10 bits when
10-bit mode is enabled) of data from the SERDES
into the RxIn input registers on the positive edge of
the clock. The RxClk125 signal is made available to
the customizable section. RxClk125 is divided by two
and made available to the customizable section on
the RxClk63 signal line. Both clocks use a high
speed, low skew clock network. Again you will most
likely want to use the RxClk63 signal to clock all reg-
isters and FIFOs in the receive data path. Registers
using RxClk125 and RxClk63 should be sensitive to
the rising edge of these clocks.
Once the data on the RxIn signal lines is latched into
the input registers, the data is passed on to the 8b/
10b decoder. Under standard operation, (input RxRa-
wEn is low), the data is decoded into 4, 8-bit charac-
ters and the resulting Fibre Channel word is placed
on the RxData[31:0] output signals. RxRData is not
used under normal operation. If the decoder detects a
Fibre Channel comma character in the most signifi-
cant character of the word, the RxKChar signal line
will be asserted.
When the RxCrcEn signal is asserted the CRC check-
ing logic will function. The CRC logic will automati-
cally detect a SOF word and begin performing CRC
division on the next word in the data stream using the
ANSI specified CRC polynomial for Fibre Channel.
When an EOF word or any other FC ordered set is
detected (unless RxIFIdleEn is asserted, then the IDLE
ordered set will be ignored by the CRC checker) the
CRC will assert the RxCrcRdy signal for one cycle of
the RxClk63 clock. If the remainder for the division is
zero, the RxCrcOK signal line will also be asserted
during this same cycle.
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