USS344 データシートの表示（PDF） - Agere -> LSI Corporation

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USS344

USS-344 QuadraBus™ Four-Host PCI-to-USB OpenHCI Host Controller

Agere -> LSI Corporation 

Advance Data Sheet, Rev. 9

June 2001

USS-344 QuadraBus

Four-Host PCI-to-USB OpenHCI Host Controller

PCI Registers (continued)

Table 47. Expansion ROM Base Address Register (30h—33h)

Expansion ROM not supported by the USS-344.

Bits

31:0

Field

Expansion ROM Base R

Address

Read/Write

Reset/Description

00000000h

Table 48. Capabilities Pointer Register (34h)

Bits

7:0

Field

Cap_Ptr

Read/Write

R

Reset/Description

TEST1 = 0b: 50h

TEST1 = 1b: 00h

Table 49. Interrupt Line Register (3Ch)

Bits

7:0

Field

Interrupt Line

Read/Write

R/W

Reset/Description

00h

Table 50. Interrupt Pin Register (3Dh)

If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core.

If TEST0 = 1b, interrupt B is used as the PCI interrupt for this core.

Bits

7:0

Field

Interrupt Pin

Read/Write

R

Reset/Description

TEST0 = 0b: 01h

TEST0 = 1b: 02h

Table 51. Min_Gnt Register (3Eh)

The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns.

Bits

7:0

Field

Min_Gnt

Read/Write

R

Reset/Description

03h

Table 52. Max_Lat Register (3Fh)

The USS-344 requires service at a minimum interval of 21.3 µs.

Bits

7:0

Field

Max_Lat

Read/Write

R

Reset/Description

56h

Table 53. Special—Subsystem Write Capability (4Ch)

This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0

is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID

registers (refer to Tables 23 and 24).

Bits

31:1

0

Field

Reserved

Subsystem Write

Read/Write

R

R/W

Reset/Description

00000000h

0b

0 = Subsystem write disabled

1 = Subsystem write enabled

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