USS344 データシートの表示（PDF） - Agere -> LSI Corporation
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USS344 Datasheet PDF : 54 Pages
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Advance Data Sheet, Rev. 9
June 2001
USS-344 QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 14. Revision ID Register (08h)
Represents the current revision of the USS-344.
Bits
Field
Read/Write
Reset/Description
7:0
Revision ID*
R
10h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified
electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by phys-
ical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be
printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 15. Class Code Register (09h—0Bh)
The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification.
Bits
7:0
15:8
23:16
Field
Programming Interface R
Subclass
R
Base Class
R
Read/Write
Reset/Description
10h = OpenHCI Host Controller
03h = Universal Serial Bus
0Ch = Serial Bus Controller
Table 16. Cache Line Size Register (0Ch)
No cache line is supported by the USS-344.
Bits
7:0
Field
Cache Line Size
Read/Write
R
Reset/Description
00h
Table 17. Latency Timer Register (0Dh)
Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master.
Bits
7:0
Field
Latency Timer
Read/Write
R/W
Reset/Description
Upper 5 bits are read/write. Lower
3 bits are read only.
Table 18. Header Type Register (0Eh)
The USS-344 supports PCI header type 0 only.
Bits
7:0
Field
Header Type
Read/Write
R
Reset/Description
80h = Multifunction PCI Device
Table 19. BIST Register (0Fh)
BIST is not supported by the USS-344.
Bits
7:0
BIST
Field
Read/Write
R
Reset/Description
00h
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