Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
Tables
List of Tables (continued)
Page
Table 51. ITU HDB3 Coding and DCPAT Binary Coding ...................................................................................... 90
Table 52. XCLK (16x, CLKS = 0) Timing Specifications........................................................................................ 91
Table 53. XCLK (1x, CLKS = 1) Timing Specifications.......................................................................................... 92
Table 54. XCLK Specifications .............................................................................................................................. 92
Table 55. Termination Components by Application............................................................................................... 94
Table 56. Absolute Maximum Ratings................................................................................................................... 95
Table 57. ESD Threshold Voltage ......................................................................................................................... 95
Table 58. Recommended Operating Conditions ................................................................................................... 95
Table 59. Power Consumption .............................................................................................................................. 96
Table 60. Power Dissipation.................................................................................................................................. 96
Table 61. Logic Interface Characteristics .............................................................................................................. 96
Table 62. Data Interface Timing ............................................................................................................................ 97
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