TLIU04C1 データシートの表示（PDF） - Agere -> LSI Corporation

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TLIU04C1

Quad T1/E1 Line Interface

Agere -> LSI Corporation 

TLIU04C1 Quad T1/E1 Line Interface

Advance Data Sheet, Rev. 2

April 1999

Tables

List of Tables

Page

Table 1. Pin Descriptions....................................................................................................................................... 10

Table 2. System Interface Pin Mapping................................................................................................................. 14

Table 3. Microprocessor Configuration Modes...................................................................................................... 14

Table 4. MODE [1—4] Microprocessor Pin Definitions.......................................................................................... 15

Table 5. Microprocessor Input Clock Specifications.............................................................................................. 16

Table 6. LIU Register Bank ................................................................................................................................... 17

Table 7. Register Map for CODE Bits.................................................................................................................... 20

Table 8. Digital Loss of Signal Standard Select .................................................................................................... 22

Table 9. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) ................................ 22

Table 10. DS1 RLIU Specifications ....................................................................................................................... 23

Table 11. CEPT RLIU Specifications..................................................................................................................... 26

Table 12. Equalizer/Rate Control .......................................................................................................................... 29

Table 13. Register Map for CODE Bits.................................................................................................................. 30

Table 14. DSX-1 Pulse Template Corner Points (from CB119) ............................................................................ 31

Table 15. DS1 Transmitter Specifications ............................................................................................................. 32

Table 16. CEPT Transmitter Specifications........................................................................................................... 34

Table 17. Loopback Control .................................................................................................................................. 41

Table 18. AMI Encoding ........................................................................................................................................ 43

Table 19. DS1 B8ZS Encoding.............................................................................................................................. 43

Table 20. ITU HDB3 Coding and DCPAT Binary Coding ...................................................................................... 43

Table 21. Alarm Registers ..................................................................................................................................... 44

Table 22. Alarm Mask Registers ........................................................................................................................... 45

Table 23. Global Control Register (0100).............................................................................................................. 45

Table 24. Global Control Register (0101).............................................................................................................. 46

Table 25. Channel Configuration Registers (0110—1001).................................................................................... 46

Table 26. Channel Configuration Register (1011) ................................................................................................. 47

Table 27. Control Register (1100) ......................................................................................................................... 47

Table 28. XCLK (16x, CLKS = 0) Timing Specifications ....................................................................................... 48

Table 29. XCLK (1x, CLKS = 1) Timing Specifications ......................................................................................... 49

Table 30. Termination Components by Application............................................................................................... 50

Table 31. Absolute Maximum Ratings................................................................................................................... 51

Table 32. ESD Threshold Voltage ......................................................................................................................... 51

Table 33. Recommended Operating Conditions ................................................................................................... 51

Table 34. Power Consumption .............................................................................................................................. 52

Table 35. Power Dissipation.................................................................................................................................. 52

Table 36. Logic Interface Characteristics .............................................................................................................. 52

Table 37. Microprocessor Interface I/O Timing Specifications .............................................................................. 53

Table 38. Data Interface Timing ............................................................................................................................ 59

Table 39. Pin Descriptions..................................................................................................................................... 62

Table 40. System Interface Pin Mapping............................................................................................................... 66

Table 41. Digital Loss of Signal Standard Select .................................................................................................. 70

Table 42. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) .............................. 71

Table 43. DS1 RLIU Specifications ....................................................................................................................... 72

Table 44. CEPT RLIU Specifications..................................................................................................................... 75

Table 45. Equalizer/Rate Control .......................................................................................................................... 78

Table 46. DSX-1 Pulse Template Corner Points (from CB119) ............................................................................ 80

Table 47. DS1 Transmitter Specifications ............................................................................................................. 80

Table 48. CEPT Transmitter Specifications........................................................................................................... 82

Table 49. AMI Encoding ........................................................................................................................................ 90

Table 50. DS1 B8ZS Encoding.............................................................................................................................. 90

6

Lucent Technologies Inc.

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