MC44871DTB データシートの表示（PDF） - Motorola => Freescale
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MC44871DTB Datasheet PDF : 12 Pages
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MC44871
Bit T13: Switches the Band Buffer Output to Test Mode
T13 = 0
Normal Operation
=1
Test Mode: Fref Out at B2 Fby2 Out at B1
In the test mode, B2 and B1 have to be ON (B2=B1=1).
Fref is the reference frequency. Fby2 is the output frequency of
the programmable divider divided–by–2.
Bit T14: Controls the Charge Pump Current
T14 = 0
Pump Current 5.0 µA
=1
Pump Current 20 µA
Bit AD2, AD1, AD0: Indicate the ADC Pin Analog Level
ADC Input Voltage
AD2 AD1 AD0
0 to 0.18 VCC
0.18 to 0.34 VCC
0.34 to 0.5 VCC
0.5 to 0.66 VCC
0.66 to 0.82 VCC
0.82 to 1.0 VCC
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
Bit LO: Indicates the Status of Lock Detetector
LO = 0
PLL Status Not Locked
LO = 1
PLL Status Locked
Figure 6. Equivalent Circuit of the Integrated
PNP Band Buffers
VCC
IB
“On”/“Off”
IB + ISUB = 5.5 mA Typical
IB = Base Current
ISUB = Substrate Current of PNP
Saturation Voltage
0.2 V Typical
0.5 V Max
ISUB
Out
B0…B2
30 mA (40 mA
at 0 to 80°C)
Figure 7. Equivalent Circuit of the Integrated
NPN Band Buffer
VCC = 5.0 V
IB1
Out B4
200
IB2
Protection 20...25 V 1.2 V typ
IB3
@ 5.0 mA
”On”/”Off”
IB1 + IB2 + IB3 = 0.5 mA Typ
IB = Base Current
OPERATING DESCRIPTION
Introduction
A representative block diagram and typical system
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
Minimum Ratio 256
N0 … N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The divide–by–8 prescaler has a preamplifier which
guarantees high input sensitivity.
The Phase Comparator
The phase comparator is both phase and frequency
sensitive and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
output (Pin 1) needs an external 750 kΩ pull–up resistor (560
kΩ minimum). This minimum value is defined by the charge
pump output current capability.
The Oscillator
The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground
in series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 15 has low amplitude and low harmonic
distortion.
Power Dissipation
The typical power dissipation of the circuit is about
200 mW (VTUN = 15 V with external pull–up of 560 kΩ, one
buffer “On” at 30 mA). It is calculated with the following
formula:
+ ǒ Ǔ ) * PD
VCC x ICC
W VPin2 VTUN
560 k
x VTUN
) ǒ Ǔ Vsat x IOut buffer
) Example: (5 x 38)
32 – 15
5.6 x 105
x
15
) + (0.20 x 30) 197 mW
MOTOROLA ANALOG IC DEVICE DATA
9
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