DS1215 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS1215 Datasheet PDF : 15 Pages
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RAM/TIME CHIP INTERFACE Figure 3
CMOS STATIC RAM
A0 – AN
ADD
DATA I/O
WE
D0 – D7
OE
CE
VCC
CE
RST
+
BAT1
DS1215
10
15
CEO VCCO
12
6
OE
D
3
7
WE
Q
11
CEI
VCCI
13
ROM/ 9
RST
4
RAM 14
BAT1
BAT2
X1
X2
1
2
32.768 KHz
+5 VDC
+
BAT2
OR TIE TO GND FOR
ONE–BATTERY
OPERATION
DS1215
ROM/TIME CHIP INTERFACE Figure 4
ROM
A0 – AN
ADD
VCC
DATA I/O
A2
OE
OE
A0
CE
D0 – D7
CE
RST
+
BAT1
DS1215
6
D
12
OE
3
WE
10
CEO
7
Q
16
VCCI
11
CEI
VCCO 15
13
ROM/ 9
RST
4
RAM 14
BAT1
BAT2
X1
X2
1
2
32.768 KHz
+5 VDC
+
BAT2
OR TIE TO GND FOR
ONE–BATTERY
OPERATION
032697 5/15
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