DS1215 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
部品番号
コンポーネント説明
一致するリスト
DS1215 Datasheet PDF : 15 Pages
| |||
DS1215
NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within
the Time Chip is determined by the level of the
ROM/RAM select pin. When ROM/RAM is connected to
ground, the controller is set in the RAM mode and per-
forms the circuit functions required to make static
CMOS RAM and the timekeeping function nonvolatile.
A switch is provided to direct power from the battery in-
puts or VCCI to VCCO with a maximum voltage drop of
0.3 volts. The VCCO output pin is used to supply uninter-
rupted power to CMOS SRAM. The DS1215 also per-
forms redundant battery control for high reliability. On
power–fail, the battery with the highest voltage is auto-
matically switched to VCCO. If only one battery is used in
the system, the unused battery input should be con-
nected to ground.
The DS1215 safeguards the Time Chip and RAM data
by power–fail detection and write protection. Power–fail
detection occurs when VCCI falls below VTP, which is
equal to 1.26 x VBAT. The DS1215 constantly monitors
the VCCI supply pin. When VCCI is less than VTP, a com-
parator outputs a power–fail signal to the control logic.
The power–fail signal forces the chip enable output
(CEO) to VCCI or VBAT–0.2 volts for external RAM write
protection. During nominal supply conditions, CEO will
track CEI with a maximum propagation delay of 20 ns.
Internally, the DS1215 aborts any data transfer in prog-
ress without changing any of the Time Chip registers
and prevents future access until VCCI exceeds VTP. A
typical RAM/Time Chip interface is illustrated in
Figure 3.
When the ROM/RAM pin is connected to VCCO, the con-
troller is set in the ROM mode. Since ROM is a read–
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO low when
power fails. However, the Time Chip does retain the
same internal nonvolatility and write protection as de-
scribed in the RAM mode. In addition, the chip enable
output is set at a low level on power–fail as VCCI falls be-
low the level of VBAT. A typical ROM/Time Chip interface
is illustrated in Figure 4.
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in 8 registers of
8 bits, each of which is sequentially accessed one bit at
a time after the 64–bit pattern recognition sequence has
been completed. When updating the Time Chip regis-
ters, each must be handled in groups of 8 bits. Writing
and reading individual bits within a register could pro-
duce erroneous results. These read/write registers are
defined in Figure 5.
Data contained in the Time Chip registers is in binary
coded decimal format (BCD). Reading and writing the
registers is always accomplished by stepping though all
8 registers, starting with bit 0 of register 0 and ending
with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20 –23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
reset and oscillator functions. Bit 4 controls the reset pin
(Pin 13). When the reset bit is set to logic 1, the reset in-
put pin is ignored. When the reset bit is set to logic 0, a
low input on the reset pin will cause the Time Chip to
abort data transfer without changing data in the time-
keeping registers. Reset operates independently of all
other inputs. Bit 5 controls the oscillator. When set to
logic 0, the oscillator turns on and the watch becomes
operational.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that
will always read logic 0. When writing these locations,
either a logic 1 or 0 is acceptable.
032697 4/15
Share Link: 