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IP1000ALF-DS-R01 データシート - ETC2

IP1000A image

部品番号
IP1000ALF-DS-R01

コンポーネント説明

Other PDF
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page
75 Pages

File Size
1.1 MB

メーカー
ETC2
ETC2 ETC2

[IC Plus Corp.]

General Description
The IP1000A LF is a truly 10/100/1000Mbps Gigabit Ethernet NIC single chip which it incorporates a 32-bit PCI interface with bus master support. It is manufactured using standard digital CMOS process and contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT5 unshielded twisted pair cable.

Features
• PCI & DMA Features
   – PCI Specification Revision 2.3 compliant
   – 32-bit, 33/66MHz bus master capability
   – Efficient DMA operation maximizes PCI band-width utilization
   – 1 Terabyte (40 bit) address space
   – Scatter, gather transmit/receive DMA
   – Transmit "interrupt-less" mode of operation
   – Receive frame priority interrupts
   – Receive interrupt coalescing
• FIFO Features
   – No external memory required
   – Receive FIFO flow control thresholds
   – Configurable TX/RX FIFO
• MAC Features
   – IEEE 802.3z, 802.3x compliant
   – IEEE 802.1p, 802.1Q compliant
   – 1000Mbps, 100Mbps, 10Mbps triple speed, half/full duplex operation
   – Transmit and receive back to back frames at full wire speed
   – Half duplex carrier extension and packet bursting
   – Asymmetric/symmetric flow control
   – VLAN tag insertion/removal
   – VLAN tagged frame filtering
   – IPV4/6, TCP, UDP checksum calculation/ verification
   – 802.3 MIB statistic register sets
   – 64-bit hash table for multicast frame filtering
   – Jumbo frame support for transmit/receive
   – Big-endian
• Phsical Layer Features
   – Fully integrated IEEE 802.3ab compliant 1000BASE-T, 100BASE-TX and 10BASE-T port
   – DSP receiver includes feed-forward equalizer, decision feedback equalizer, echo canceller, crosstalk canceller, and baseline wander correction
   – 802.3ab compliant Auto-Negotiation for automatic speed, duplex, and master/slave configuration
   – Automatic MDI/MDI-X crossover function and polarity correction
   – Automatic pair skew adjustment
   – PHY management registers
   – Smart Cable Analyzer (SCA™)
   – Smart speed downshift
   – APS(Auto Power Saving)
      a. Power Saving with Link status detecting
      b. Keep only MAC alive through software setting
• Power Management, EEPROM and Package
   – WakeOnLAN support
   – ACPI Revision 1.0 compliant
   – 1.8/3.3V CMOS with 5V tolerant I/O
   – EEPROM 93C46 support
   – Optional boot from serial ROM support
   – 128-pin LQFP with e-PAD package
• Support Lead Free package (Please refer to the Order Information)

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部品番号
コンポーネント説明
PDF
メーカー
Single Chip Fast Ethernet NIC Controller
Unspecified
Single Chip Fast Ethernet NIC controller
Davicom Semiconductor, Inc.
Single Chip Fast Ethernet NIC Controller
Davicom Semiconductor, Inc.
Single Chip Fast Ethernet NIC controller
Unspecified
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
Macronix International
Single Chip Fast Ethernet NIC Controller
Davicom Semiconductor, Inc.
Single Chip Fast Ethernet NIC Controller
Davicom Semiconductor, Inc.
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
Macronix International
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
Macronix International
3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER
Macronix International

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