L5950 データシートの表示（PDF） - STMicroelectronics
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L5950 Datasheet PDF : 8 Pages
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L5950
Figure 2. Typical Application Circuit.
EN
FBATT
0.1µF
1000µF
ENABLE
BAT
VREF
VREF
SCL
SDA
GND
REG1
REG2
REG3
REG4
REG4
REG5 REG5
C14
10µF
C12
10µF
HSD1
HSD2
HSD3
HSD1
HSD2
HSD3
D99AU1010A
REG3
C10
10µF
REG2
C8
10µF
REG1
C6
10µF
(*) ESR of output capacitors should be between 0.1Ω and 5.0Ω.
WRITE MODE:
CHIP ADDRESS
DATA BYTE
S
0A
A .. .. P
MSB
LSB
MSB
LSB
S = START condition - SDA goes from high to low while SCL is high
A = Acknowledge - the device being written to, pulls down on data line (SDA) during the acknowledge
clock pulse.
P = STOP condition - SDA goes from low to high while SCL is high.
CHIP ADDRESS BYTE:
CHIP ADDRESS
READ/WRITE
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
0
0
0
0
DATA BYTE:
DATA BYTE
REG1
R4 10V
REG4
REG5
HSD1
HSD2
HSD3
b7
b6
b5
b4
b3
b2
b1
b0
X
Default mode is 0000 0000 which corresponds to all outputs being off, low power mode.
Bit 5 Controls the output voltage of REG4. A ’0’ corresponds to 8V and a ’1’ corresponds to 10V.
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