AD660(2008) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
一致するリスト
AD660 Datasheet PDF : 20 Pages
| |||
AD660
THEORY OF OPERATION
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to the
applied digital word, ranging from 0 mA to 2 mA. A segmented
architecture is used, where the most significant four data bits
are thermometer decoded to drive 15 equal current sources.
The lesser bits are scaled using a R-2R ladder, then applied
together with the segmented sources to the summing node of
the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to 10 V
span, or it can be connected to the reference input to provide a
−10 V to +10 V span.
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
15
14 12
11
5
HBE 16
SER 17
CLR 18
LDAC 19
CONTROL
LOGIC
16-BIT LATCH
16-BIT LATCH
AD660
10kΩ
10.05kΩ
13 SOUT
SPAN/
22 BIPOLAR
OFFSET
REF IN 23
10kΩ
16-BIT DAC
21 VOUT
10V REF
20 AGND
24
1
REF OUT –VEE
2
+VCC
3
+VLL
4
DGND
Figure 7. Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 can be connected
to produce a unipolar output range of 0 V to 10 V or a bipolar
output range of −10 V to +10 V. Gain and offset drift are mini-
mized in the AD660 because of the thermal tracking of the
scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 8 provides a unipolar 0 V to
10 V output range. In this mode, 50 Ω resistors are tied between
the SPAN/BIPOLAR OFFSET terminal (Pin 22) and VOUT (Pin 21),
and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible
to use the AD660 without any external components by tying Pin 24
directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating
these resistors increases the gain error by 0.25% of FSR.
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
15
14 12
11
5
HBE 16
SER 17
CLR 18
LDAC 19
REF IN
23
CONTROL
LOGIC
10kΩ
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
AD660
SOUT 13
10kΩ
SPAN/
BIPOLAR
OFFSET
22
10.05kΩ
R2
50Ω
VOUT
21
OUTPUT
10V REF
20 AGND
REF OUT
24
R1
50Ω
1
–VEE
2
+VCC
3
4
+VLL DGND
Figure 8. 0 V to 10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this
can be accomplished using the circuit shown in Figure 9. The
adjustment procedure is as follows:
1. Zero adjust.
Turn all bits off and adjust the zero trimmer, R4, until the
output reads 0.000000 V (1 LSB = 153 μV).
2. Gain adjust.
Turn all bits on and adjust the gain trimmer, R1, until the
output is 9.999847 V. (Full scale is adjusted to 1 LSB less
than the nominal full scale of 10.000000 V.)
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
15
14 12
11
5
HBE 16
SER 17
CONTROL
LOGIC
CLR 18
LDAC 19
REF IN
23
10kΩ
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
AD660
SOUT 13
SPAN/
BIPOLAR
10kΩ OFFSET
22
10.05kΩ
R2
50Ω
+VCC
R3
16k R4
10k
–VEE
VOUT
21
OUTPUT
10V REF
20 AGND
REF OUT
24
1
–VEE
2
+VCC
3
4
+VLL DGND
R1
100Ω
Figure 9. 0 V to 10 V Unipolar Voltage Output with Gain and Offset
Adjustment
Rev. B | Page 10 of 20
Share Link: 