UDA1328T データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

UDA1328T

Multi-channel filter DAC

Philips Electronics 

Philips Semiconductors

Multi-channel filter DAC

Preliminary specification

UDA1328T

7 PINNING

SYMBOL

VOUT3

VOUT4

VSSA

VOUT5

VOUT6

VDDA

n.c.

TEST3

STATIC

BCK

WS

DATAI12

DATAI34

DATAI56

n.c.

SYSCLK

L3MODE

L3CLOCK

L3DATA

VSSD

VDDD

TEST2

MUTE

DEEM1

DEEM0

DS

TEST1

VOUT1P

VOUT1N

Vref

VOUT2N

VOUT2P

PIN

DESCRIPTION

1 channel 3 analog output

2 channel 4 analog output

3 analog ground

4 channel 5 analog output

5 channel 6 analog output

6 analog supply voltage

7 not connected (reserved)

8 test output 3

9 static mode/L3 mode switch input

10 bit clock input

11 word select input

12 data input channel 1 and 2

13 data input channel 3 and 4

14 data input channel 5 and 6

15 not connected (reserved)

16 system clock: 256fs, 384fs,

512fs and 768fs

17 L3 mode selection input

18 L3 clock input

19 L3 data input

20 digital ground

21 digital supply voltage

22 test output 2

23 static mute control input

24 DEEM control 1 input

(static mode)

25 L3 address select

(L3 mode)/DEEM control 0 input

(static mode)

26 digital silence detect output

27 test input 1

28 channel 1 analog output P

29 channel 1 analog output N

30 DAC reference voltage

31 channel 2 analog output N

32 channel 2 analog output P

handbook, halfpage

VOUT3 1

VOUT4 2

VSSA 3

VOUT5 4

VOUT6 5

VDDA 6

n.c. 7

TEST3 8

STATIC 9

BCK 10

WS 11

DATAI12 12

DATAI34 13

DATAI56 14

n.c. 15

SYSCLK 16

32 VOUT2P

31 VOUT2N

30 Vref

29 VOUT1N

28 VOUT1P

27 TEST1

26 DS

25 DEEM0

UDA1328T

24 DEEM1

23 MUTE

22 TEST2

21 VDDD

20 VSSD

19 L3DATA

18 L3CLOCK

17 L3MODE

MGR980

Fig.2 Pin configuration.

2000 Jan 04

6

Share Link: