ADSP-2189NKCAZ-320 データシートの表示（PDF） - Analog Devices
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ADSP-2189NKCAZ-320 Datasheet PDF : 48 Pages
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ADSP-218xN
Table 9. Common-Mode Pins (Continued)
Pin Name
No. of Pins I/O
Function
VDDINT
VDDEXT
GND
4
I
Internal VDD (1.8 V) Power (BGA)
7
I
External VDD (1.8 V, 2.5 V, or 3.3 V) Power (BGA)
20
I
Ground (BGA)
EZ-Port
9
I/O
For Emulation Use
1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices or set as a programmable flag.
2 SPORT configuration determined by the DSP System Control Register. Software configurable.
MEMORY INTERFACE PINS
ADSP-218xN series members can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities.
The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. Table 10 and Table 11 list the active signals at specific
pins of the DSP during either of the two operating modes (Full
Memory or Host). A signal in one table shares a pin with a sig-
nal from the other table, with the active signal determined by
the mode that is set. For the shared pins and their alternate sig-
nals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on
Page 41 and Table 28 on Page 43.
Table 10. Full Memory Mode Pins (Mode C = 0)
Pin Name
A13 – 0
D23 – 0
No. of Pins I/O
14
O
24
I/O
Function
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory
Addresses.)
Table 11. Host Mode Pins (Mode C = 1)
Pin Name
No. of Pins I/O
Function
IAD15 – 0
16
A0
1
I/O
IDMA Port Address/Data Bus
O
Address Pin for External I/O, Program, Data, or Byte Access1
D23 – 8
16
I/O
Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR
1
I
IDMA Write Enable
IRD
1
I
IDMA Read Enable
IAL
1
I
IDMA Address Latch Pin
IS
1
I
IDMA Select
IACK
1
O
IDMA Port Acknowledge Configurable in Mode D; Open Drain
1 In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
TERMINATING UNUSED PINS
Table 12 shows the recommendations for terminating unused
pins.
Table 12. Unused Pin Terminations
Pin Name1
XTAL
CLKOUT
A13–1 or
IAD12 – 0
A0
I/O
3-State
(Z)2
O
O
O (Z)
I/O (Z)
O (Z)
Reset
State
O
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z3 Caused By
BR, EBR
IS
BR, EBR
Unused Configuration
Float
Float4
Float
Float
Float
Rev. A | Page 19 of 48 | August 2006
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