BR24T256FJ-W データシートの表示（PDF） - ROHM Semiconductor
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BR24T256FJ-W Datasheet PDF : 34 Pages
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BR24T256-W
Datasheet
Read Command
1. Read Cycle
Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random read
cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a command
to read data of internal address register without designating an address, and is used when to verify just after write cycle.
In both the read cycles, sequential read cycle is available where the next address data can be read in succession.
SDA
LINE
S
W
S
T
R
T
R
S
A
R
T
SLAVE
ADDRESS
I
T
E
1st WORD
ADDRESS(n)
2nd WORD
ADDRESS(n)
A
R
T
SLAVE
ADDRESS
E
A
D
DATA(n)
T
O
P
1 0 1 0 A2 A1 A0
WAWAWAWA
* 14 13 12 11
WA
0
1 0 1 0 A2 A1A0
D7
D0
00
00
RA
A
A
RA
A
/C
C
C
/C
C
WK
K
K
WK
K
Figure 37. Random Read Cycle
SDA
LINE
S
T
R
A
E
R SLAVE
A
T ADDRESS D
1 0 1 0 A2A1A0
S
T
O
DATA(n)
P
D7
D0
0
RA
A
/C
C
WK
K
Figure 38. Current Read Cycle
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1A0 D7
DATA(n)
D0
S
T
DATA(n+x)
O
P
D7
D0
00
RA
A
A
A
/C
C
C
C
WK
K
K
K
Figure 39. Sequential Read Cycle (in the case of current read cycle)
* Don’t Care bit
(1) In random read cycle, data of designated word address can be read.
(2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output.
(3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
(4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to ‘H’
while SCL signal is 'H'.
(5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. To end read command cycle, be sure to input 'H' to ACK signal
after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'.
(6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is asserted
from ‘L’ to ‘H’ while SCL signal is 'H'.
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TSZ22111 • 15 • 001
15/31
TSZ02201-0R2R0G100140-1-2
17.Dec.2018 Rev.004
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