PMS152-S14 データシートの表示（PDF） - Unspecified
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PMS152-S14 Datasheet PDF : 91 Pages
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PMS152
8bit OTP Type SuLED IO Controller
6.10. Port A Digital Input Enable Register (padier), IO address = 0x0d ..........................................63
6.11. Port B Digital Input Enable Register (pbdier), IO address = 0x0e ..........................................64
6.12. Port A Data Register (pa), IO address = 0x10 .......................................................................64
6.13. Port A Control Register (pac), IO address = 0x11 .................................................................64
6.14. Port A Pull-High Register (paph), IO address = 0x12 ............................................................64
6.15. Port B Data Register (pb), IO address = 0x14 .......................................................................64
6.16. Port B Control Register (pbc), IO address = 0x15 .................................................................64
6.17. Port B Pull-High Register (pbph), IO address = 0x16 ............................................................65
6.18. Comparator Control Register (gpcc), IO address = 0x18.......................................................65
6.19. Comparator Selection Register (gpcs), IO address = 0x19....................................................65
6.20. Timer2 Control Register (tm2c), IO address = 0x1c ..............................................................66
6.21. Timer2 Scalar Register (tm2s), IO address = 0x17................................................................66
6.22. Timer2 Counter Register (tm2ct), IO address = 0x1d ............................................................67
6.23. Timer2 Bound Register (tm2b), IO address = 0x09 ...............................................................67
6.24. PWMG0 control Register (pwmg0c), IO address = 0x20 .......................................................67
6.25. PWMG Clock Register (pwmgclk), IO address = 0x21 ..........................................................68
6.26. PWMG0 Duty Value High Register (pwmg0dth), IO address = 0x22 .....................................68
6.27. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23 .......................................68
6.28. PWMG Counter Upper Bound High Register (pwmgcubh ), IO address = 0x24 ....................68
6.29. PWMG Counter Upper Bound Low Register (pwmgcubl ), IO address = 0x25 ......................68
6.30. PWMG1 control Register (pwmg1c), IO address = 0x26 .......................................................69
6.31. PWMG1 Duty Value High Register (pwmg1dth), IO address = 0x28 .....................................69
6.32. PWMG1 Duty Value Low Register (pwmg1dtl), IO address = 0x29 .......................................69
6.33. PWMG2 control Register (pwmg2c), IO address = 0x2C.......................................................70
6.34. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2E .....................................70
6.35. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2F .......................................70
7. Instructions ......................................................................................................................... 71
7.1. Data Transfer Instructions .....................................................................................................72
7.2. Arithmetic Operation Instructions ..........................................................................................75
7.3. Shift Operation Instructions ...................................................................................................77
7.4. Logic Operation Instructions..................................................................................................78
7.5. Bit Operation Instructions ......................................................................................................81
7.6. Conditional Operation Instructions ........................................................................................82
7.7. System control Instructions ...................................................................................................83
7.8. Summary of Instructions Execution Cycle .............................................................................84
7.9. Summary of affected flags by Instructions.............................................................................85
7.10. BIT definition.........................................................................................................................85
©Copyright 2020, PADAUK Technology Co. Ltd
Page 5 of 91
PDK-DS-PMS152-EN_V105 –Jun. 9, 2020
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