ADSP-21371KSWZ-2A2 データシートの表示（PDF） - Analog Devices
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ADSP-21371KSWZ-2A2 Datasheet PDF : 52 Pages
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ADSP-21371/ADSP-21375
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral (Compatible) Interface
The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface ports (SPIs). The SPI is an industry-
standard synchronous serial link, enabling the SPI-compatible
ports of the processors to communicate with other SPI compati-
ble devices. The SPI consists of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a mas-
ter or slave device.
The SPI-compatible peripheral implementation also features
programmable baud rates and clock phases and polarities. The
SPI-compatible port uses open drain drivers to support a multi-
master configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface stan-
dard. The UART port also includes support for 5 to 8 data bits, 1
or 2 stop bits, and none, even, or odd parity. The UART port
supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable. The port:
• Supports bit rates ranging from (fPCLK/1,048,576) to
(fPCLK/16) bits per second.
• Supports data formats from 7 to 12 bits per frame.
• Can be configured to generate maskable interrupts for both
transmit and receive operations.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Peripheral Timers
Two general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables the general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
• Digital filtering and timed event processing
• 7-bit addressing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA and con-
trols the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the ADSP-2137x processor’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
port (PDAP), or the UART (see Table 7).
Table 7. DMA Channels
Peripheral
SPORT
PDAP
SPI
UART
EP
MTM/DTCP
Total DMA Channels
ADSP-21371
16
8
2
2
2
2
32
ADSP-21375
8
8
2
2
2
2
24
Rev. C | Page 10 of 52 | September 2009
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