ADSP-BF518KSWZ-ENG データシートの表示（PDF） - Analog Devices

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ADSP-BF518KSWZ-ENG

Blackfin Embedded Processor

Analog Devices 

Preliminary Technical Data

mode. In single update mode the duty cycle values are program-

mable only once per PWM period, so that the resultant PWM

patterns are symmetrical about the midpoint of the PWM

period. In the double update mode, a second updating of the

PWM registers is implemented at the midpoint of the PWM

period. In this mode, it is possible to produce asymmetrical

PWM patterns that produce lower harmonic distortion in

3-phase PWM inverters.

GENERAL-PURPOSE (GP) COUNTER

A 32-bit GP counter is provided that can sense 2-bit quadrature

or binary codes as typically emitted by industrial drives or man-

ual thumb wheels. The counter can also operate in general-

purpose up/down count modes. Then, count direction is either

controlled by a level-sensitive input signal or by two edge

detectors.

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three signals have a programmable debouncing

circuit.

An internal signal forwarded to the GP timer unit enables one

timer to measure the intervals between count events. Boundary

registers enable auto-zero operation or simple system warning

by interrupts when programmable count values are exceeded.

SERIAL PORTS

The ADSP-BF512/BF514/BF516/BF518(F) processors incorpo-

rate two dual-channel synchronous serial ports (SPORT0 and

SPORT1) for serial and multiprocessor communications. The

SPORTs support the following features:

• I2S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive signals, enabling eight

channels of I2S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

ADSP-BF512/BF514/BF516/BF518 (F)

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The processors have two SPI-compatible ports (SPI0 and SPI1)

that enable the processor to communicate with multiple SPI-

compatible devices.

The SPI interface uses three signals for transferring data: two

data signals (master output-slave input–MOSI, and master

input-slave output–MISO) and a clock signal (serial

clock–SCK). An SPI chip select input signal (SPIxSS) lets other

SPI devices select the processor, and multiple SPI chip select

output signals let the processor select other SPI devices. The SPI

select signals are reconfigured general-purpose I/O signals.

Using these signals, the SPI port provides a full-duplex, syn-

chronous serial interface, which supports both master/slave

modes and multimaster environments.

The SPI port baud rate and clock phase/polarities are program-

mable, and it has an integrated DMA channel, configurable to

support transmit or receive data streams. The SPI’s DMA chan-

nel can only service unidirectional accesses at any given time.

The SPI port clock rate is calculated as:

SPI Clock Rate

=

------------f--S--C----L--K-------------

2 × SPI_BAUD

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS

The ADSP-BF512/BF514/BF516/BF518(F) processors provide

two full-duplex universal asynchronous receiver/transmitter

(UART) ports, which are fully compatible with PC-standard

UARTs. Each UART port provides a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA-sup-

ported, asynchronous transfers of serial data. A UART port

Rev. PrE | Page 11 of 62 | March 2009

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