UPD78064YGF-XXX-3BA(1992) データシートの表示（PDF） - NEC => Renesas Technology
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UPD78064YGF-XXX-3BA Datasheet PDF : 42 Pages
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mPD78062Y,78063Y,78064Y
OVERVIEW OF FUNCTION
Item
Product Name
mPD78062Y
mPD78063Y
mPD78064Y
Internal ROM
memory Internal high-speed RAM
LCD display RAM
General registers
Instruction cycle
When main system clock
selected
When subsystem clock
selected
Instruction set
16K bytes
24K bytes
32K bytes
512 bytes
1024 bytes
40 ¥ 4 bits
8 bits ¥ 32 registers (8 bits ¥ 8 registers ¥ 4 banks)
On-chip instruction execution time cycle modification function
0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms/12.8 ms (at 5.0 MHz operation)
122 ms (at 32.768 kHz operation)
• 16-bit operation
• Multiplication/division (8 bits ¥ 8 bits,16 bits “ 8 bits)
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
I/O ports
(including segment signal output
pins)
Total
• CMOS input
• CMOS I/O
: 57
: 02
: 55
A/D converter
• 8-bit resolution ¥ 8 channels
• Segment signal output : Maximum 40
LCD controller/driver
• Common signal output : Maximum 4
• Bias
: 1/2 or 1/3 switchable
Serial interface
• 3-wired/2-wired/I2C bus mode selectable: 1 channel
H
• 3-wired/UART mode selectable
: 1 channel
• 16-bit timer/event counter : 1 channel
Timer
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
3 ( one 14-bit PWM output capability)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock 5.0 MHz operation)
32.7 kHz (at subsystem clock 32.768 kHz operation)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation)
Vectored
interrupts
Test input
Maskable
interrupts
Non-maskable
interrupts
Software
interrupts
Internal : 12, external : 6
Internal : 1
Internal : 1
Internal: 1, External: 1
Operating voltage range
VDD = 2.0 to 6.0 V
H
Package
• 100-pin plastic QFP (Fine pitch)( 14 mm)
• 100-pin plastic QFP (14 ¥ 20 mm)
3
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