V437216C04VDTG-75 データシートの表示（PDF） - Mosel Vitelic Corporation

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V437216C04VDTG-75

3.3 VOLT 16M x 72 HIGH PERFORMANCE PC133 REGISTER PLL ECC SDRAM MODULE

Mosel Vitelic Corporation  

MOSEL VITELIC

SPD-Table for 75 modules: (Continued)

Byte Number Function Described

31

Module Bank Density (Per Bank)

32

SDRAM Input Setup Time

33

SDRAM Input Hold Time

34

SDRAM Data Input Setup Time

35

SDRAM Data Input Hold Time

62-61

Superset Information (May be used in Future)

62

SPD Revision

63

Checksum for Bytes 0 - 62

64

Manufacturer’s JEDEC ID Code

65-71

Manufacturer’s JEDEC ID Code (cont.)

72

Manufacturing Location

73-90

Module Part Number (ASCII)

91-92

PCB Identification Code

93

Assembly Manufacturing Date (Year)

94

Assembly Manufacturing Date (Week)

95-98

Assembly Serial Number

99-125

Reserved

126

Intel Specification for Frequency

127

Reserved

128+

Unused Storage Location

DC Characteristics

TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V

Symbol Parameter

VIH

Input High Voltage

VIL

Input Low Voltage

VOH

Output High Voltage (IOUT = –4.0 mA)

VOL

Output Low Voltage (IOUT = 4.0 mA)

II(L)

Input Leakage Current, any input

(0 V < VIN < 3.6 V, all other inputs = 0V)

IO(L)

Output leakage current

(DQ is disabled, 0V < VOUT < VCC)

V437216C04VDTG-75

SPD Entry Value

128 MByte

1.5 ns

0.8 ns

1.5 ns

0.8 ns

Revision 2

Mosel Vitelic

V437216C04VDTG-75

Hex Value

16Mx72

20

15

08

15

08

00

02

C6

40

00

00

64

8D

00

Limit Values

Min.

Max.

2.0

–0.3

V CC +0.3

0.8

2.4

—

—

0.4

–10

10

–10

10

Unit

V

V

V

V

µA

µA

V437216C04VDTG-75 Rev. 1.2 July 2001

5

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