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V43728S04VTG-10PC データシートの表示(PDF) - Mosel Vitelic Corporation

部品番号
コンポーネント説明
一致するリスト
V43728S04VTG-10PC
Mosel-Vitelic
Mosel Vitelic Corporation  Mosel-Vitelic
V43728S04VTG-10PC Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
MOSEL VITELIC
V43728S04V(C)TG-10PC
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
SPD-Table:
written into the E2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
Byte
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Function Described
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses (for x8 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (continued)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay from Back to Back Random
Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle Time at CAS Latency = 2
Maximum Data Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active Delay tRRD
Minimum RAS to CAS Delay tRCD
SPD Entry Value
128
256
SDRAM
12
9
1
72
0
LVTTL
10.0 ns
6.0 ns
Ecc
Self-Refresh, 15.6µs
x8
n/a / x8
tccd = 1 CLK
1, 2, 4, 8 & full Page
4
CL = 2 & 3
CS Latency = 0
WL = 0
Non Buffered/Non Reg.
Vcc tol ± 10%
10.0 ns
6.0 ns
Not Supported
Not Supported
20 ns
16 ns
20 ns
Hex Value
100 MHz
-10PC
80
08
04
0C
09
01
48
00
01
A0
60
02
80
08
08
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
10
14
V43728S04V(C)TG-10PC Rev. 1.1 June 2000
4

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