INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
n PCMCIA Interface ( PCMCIA I/F )
The TX4925 has a 2 identical full PCMCIA ports.
• Provide the control signals and accepts the status signals which conform to the PCMCIA
version 2.1 standard
• Appropriate connector keying and level-shifting buffers required for 3.3V versus 5V
PCMCIA interface implementations
n Real Time Clock ( RTC )
The TX4925 has a Real Time Clock.
• 44-bit up-counter
• Interrupts on alarm, timer, and prior to RTC roll-over
• Date managed by software
n Power-down mode
The TX4925 contains support for implementation of power-down mode.
• HALT mode (stopping CPU core clock) for TX49/H2 core block
• Power-down mode (stopping input clock) for individual internal peripheral modules
• RF(Reduced Frequency) Function (1/1,1/2,1/4,1/8)
n Extended EJTAG Interface
The TX4925 contains an Extended Enhanced Joint Test Action Group ( Extended EJTAG )
interface, which provides two functions : JTAG boundary scan test that complies with
IEEE1149.1 and real-time debugging using a debug support unit ( DSU ) built into the
TX49/H2 core.
• IEEE 1149.1 JTAG Boundary Scan
• Real-time debugging functions using special emulation probe : execution control
( execution, break, step, and register / memory access ) and PC trace
EJC-TMPR4925XB -9
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION