79R4640-133DU データシートの表示（PDF） - Integrated Device Technology
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79R4640-133DU Datasheet PDF : 23 Pages
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IDT79RC4640™
Pin Description
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4640. Pin names ending with an asterisk (*) identify pins
that are active when low.
Pin
Name
Type
Description
System Bus Interface
ExtRqst*
Input
External request
Signals that the system interface needs to submit an external request.
Release*
Output
Release interface
Signals that the processor is releasing the system interface to slave state
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
ValidOut* Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the
SysCmd bus.
SysAD(31:0) Input/Output System address/data bus
A 32-bit address and data bus for communication between the processor and an external agent.
SysADC(3:0) Input/Output System address/data check bus
A 4-bit bus containing parity check bits for the SysAD bus during data bus cycles.
SysCmd(8:0) Input/Output System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
SysCmdP
Input/Output Reserved system command/data identifier bus parity
For the RC4640 this signal is unused on input and zero on output.
Clock/Control interface
MasterClock Input
Master clock
Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation
frequency is derived by multiplying this clock up by the factor selected during boot initialization.
VCCP
Input
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
VSSP
Input
Quiet VSS for PLL
Quiet VSS for the internal phase locked loop.
Interrupt interface
Int*(5:0)
Input
Interrupt
Six general processor interrupts, bit-wise OR’ d with bits 5:0 of the interrupt register.
NMI*
Input
Non-maskable interrupt
Non-maskable interrupt, OR’d with bit 6 of the interrupt register.
Initialization interface
VCCOk
Input
VCC is OK
When asserted, this signal indicates to the RC4640 that the power supply has been above Vcc minimum for more than 100 millisec-
onds and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream.
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December 5, 2008
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