WT6014 データシートの表示（PDF） - Weltrend Semiconductor

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WT6014

Digital Monitor Controller

Weltrend Semiconductor 

WT6014

Digital Monitor Controller

Ver. 1.21 Jul-31-1998

(5) Data bytes transmit/receive

If the RW bit is "1", the shift register will load data from the data buffer (REG#18H) before the

data

byte is transmitted and shift out data to the SDA pin before the rising edge of the SCL clock.

If the RW bit is "0", the shift register will shift in data on the rising edge of the SCL clock and the

whole data byte is latched to the data buffer(REG#18H).

(6) Handshaking procedure

The handshaking is done on the byte level. The DDC interface will hold the SCL pin low after the

acknowledge bit automatically. The bus master will be forced to wait until the WT6014 is ready for

the next byte transfer. To release the SCL pin, write REG#19H will release clear the wait state.

(7) Interrupt INT0

The DDC interface interrupt is enabled by setting the IEN_D bit in the REG#1AH.

Interrupt INT0 occurs when:

- Transmit buffer empty in DDC1 state.

The INT0 occurs when the shift register load data from data buffer.

Write REG#18H will clear the transmit buffer empty condition.

- Acknowledge is detected in DDC2B state.

The INT0 occurs on the falling edge of the SCL clock after the acknowledge had been

detected.

The SCL pin will be pulled low to force the bus master to wait until the REG#19H is written.

- STOP condition occurs in DDC2B state

Address R/W Initial Bit7 Bit6 Bit5 Bit4 Bit3 Bit2

0018H R/W FFH D7 D6 D5 D4 D3 D2

0019H R 40H DDC2B ADDR RW START STOP --

0019H W A0H A6 A5 A4 A3 A2 A1

Bit1 Bit0

D1 D0

--

--

A0 ENACK

Bit Name

DDC2B

ADDR

RW

START

STOP

ENACK

A6,A5, …., A0

D7,D6, …., D0

Bit value = “1”

Bit value = “0”

DDC2B state.

DDC1 state.

received address equals to the address received address equals to ‘1010000’.

in REG#19H(W).

received R/W bit is ‘1’.

received R/W bit is ‘0’.

START condition is detected.

No START condition is detected.

STOP condition is detected.

No STOP condition is detected.

Enable acknowledge.

Disable acknowledge.

7-bit slave address

Data to be transmitted or received data.

Weltrend Semiconductor, Inc.

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