CY7C1473V33(2004) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1473V33
(Rev.:2004)

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1471V33

CY7C1473V33

CY7C1475V33

1

Logic Block Diagram – CY7C1473V33 (4M x 18)

A0, A1, A

MODE

CLK

C

CE

CEN

ADDRESS

REGISTER

A1

A0

D1

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

Q1 A1'

Q0 A0'

BURST

LOGIC

ADV/LD

BWA

BWB

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

E

N

MEMORY

S

WRITE

ARRAY

E

DRIVERS

A

M

P

S

OE

CE1

READ LOGIC

CE2

CE3

ZZ

SLEEP

CONTROL

Logic Block Diagram – CY7C1471V33 (2M x 36)

A0, A1, A

MODE

CLK

C

CE

CEN

ADDRESS

REGISTER

A1

A0

D1

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

Q1

Q0

A1'

A0'

BURST

LOGIC

INPUT E

REGISTER

ADV/LD

BWA

BWB

BWC

BWD

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

S

E

N

MEMORY

S

WRITE

ARRAY

E

DRIVERS

A

M

P

S

OE

CE1

READ LOGIC

CE2

CE3

ZZ

SLEEP

CONTROL

INPUT E

REGISTER

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

E

G

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

E

G

DQs

DQPA

DQPB

DQs

DQPA

DQPB

DQPC

DQPD

Document #: 38-05288 Rev. *E

Page 2 of 29

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