CY23S08SXI-4T(2007) データシートの表示（PDF） - Cypress Semiconductor

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CY23S08SXI-4T
(Rev.:2007)

3.3V Zero Delay Buffer

Cypress Semiconductor 

CY23S08

Table 2. Select Input Decoding

S2

S1

CLOCK A1–A4

CLOCK B1–B4

0

0

Three-State

Three-State

0

1

Driven

Three-State

1

0

Driven

Driven

1

1

Driven

Driven

Table 3. Available CY23S08 Configurations

Device

Feedback From

Bank A Frequency

CY23S08–1

Bank A or Bank B

Reference

CY23S08–1H

Bank A or Bank B

Reference

CY23S08–2

Bank A

Reference

CY23S08–2H

Bank A

Reference

CY23S08–2

Bank B

2 X Reference

CY23S08–2H

Bank B

2 X Reference

CY23S08–3

Bank A

2 X Reference

CY23S08–3

Bank B

4 X Reference

CY23S08–4

Bank A or Bank B

2 X Reference

Output Source

PLL

PLL

Reference

PLL

PLL Shutdown

Y

N

Y

N

Bank B Frequency

Reference

Reference

Reference/2

Reference/2

Reference

Reference

Reference or Reference[1]

2 X Reference

2 X Reference

Spread Aware

Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been

one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the

Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant

amount of tracking skew which may cause problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with

Spread Spectrum Frequency Timing Generator (SSFTG) ICs.

Document #: 38-07265 Rev. *G

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