EVAL-AD1940AZ データシートの表示（PDF） - Analog Devices
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EVAL-AD1940AZ Datasheet PDF : 36 Pages
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD1940/AD1941
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1
MCLK 2
RESERVED 3
PLL_CTRL0 4
PLL_CTRL1 5
PLL_CTRL2 6
PLL_GND 7
PLL_VDD 8
NC 9
LRCLK_IN 10
BCLK_IN 11
GND 12
PIN 1
INDICATOR
AD1940
TOP VIEW
(Not to Scale)
36 GND
35 BCLK_OUT1
34 LRCLK_OUT1
33 ODVDD
32 SDATA_OUT3
31 SDATA_OUT2
30 SDATA_OUT1
29 SDATA_OUT0
28 ODVDD
27 BCLK_OUT0
26 LRCLK_OUT0
25 VDD
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
VDD 1
MCLK 2
RESERVED 3
PLL_CTRL0 4
PLL_CTRL1 5
PLL_CTRL2 6
PLL_GND 7
PLL_VDD 8
I2C_FILT_EN 9
LRCLK_IN 10
BCLK_IN 11
GND 12
PIN 1
INDICATOR
AD1941
TOP VIEW
(Not to Scale)
36 GND
35 BCLK_OUT1
34 LRCLK_OUT1
33 ODVDD
32 SDATA_OUT3
31 SDATA_OUT2
30 SDATA_OUT1
29 SDATA_OUT0
28 ODVDD
27 BCLK_OUT0
26 LRCLK_OUT0
25 VDD
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
NC = NO CONNECT
Figure 7. 48-Lead LQFP Pin Configuration, AD1940
Figure 8. 48-Lead LQFP Pin Configuration, AD1941
Table 10. Pin Function Descriptions
Pin No.
AD1940 AD1941 I/O
1, 25, 37 1, 25, 37
2
2
IN
3
3
4
4
IN
5
5
IN
6
6
IN
7
7
8
8
9
21, 22
9
IN
10
10
IN
11
11
IN
12, 24, 36, 12, 24, 36,
48
48
13
13
14
14
IN
15
12
IN
16
16
IN
17
17
IN
18
18
IN
19
OUT
20
IN
21
IN
Mnemonic
VDD
MCLK
RESERVED
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL_GND
PLL_VDD
NC
I2C_FILT_ENB
LRCLK_IN
BCLK_IN
GND
VDD
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
ADR_SEL
COUT
CCLK
CLATCH
Description
Core Power.
Master Clock Input.
This pin should be connected to ground.
PLL Control 0.
PLL Control 1.
PLL Control 2.
PLL Ground.
PLL Power.
No Connect.
I2C Filter Enable, Active Low.
Left/Right Clock for Serial or TDM Data Inputs.
Bit Clock for Serial or TDM Data Inputs.
Digital Ground.
Core Power.
Serial Data Input 0.
Serial Data Input 1.
Serial Data Input 2/TDM Input 1.
Serial Data Input 3/TDM Input 0.
Control Port Address Select.
SPI Data Output.
Clock for SPI.
SPI Data Latch.
Rev. B | Page 9 of 36
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