ISL9005A データシートの表示（PDF） - Renesas Electronics

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ISL9005A

LDO with Low ISUPPLY, High PSRR

Renesas Electronics 

ISL9005A

Package Outline Drawing

L8.2x3

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 3/15

2.00

A

PIN 1

INDEX AREA

B

6

1

PIN #1

INDEX AREA

2X 1.50

6X 0.50

1.80 +0.10/-0.15

(4X) 0.15

TOP VIEW

(1.65)

(1.50)

(8X 0.60)

(2.80)(1.80)

(6X 0.50)

(8X 0.25)

TYPICAL RECOMMENDED LAND PATTERN

FN6452 Rev 2.00

November 20, 2015

8X 0.40 ±0.10

8

1.65 +0.10/-0.15

BOTTOM VIEW

8X 0.25 +0.07/-0.05 4

0.10 M C A B

0.90 ±0.10

0.05 MAX

SIDE VIEW

SEE DETAIL "X"

0.10 C

BASE PLANE C

SEATING PLANE

0.08 C

0.20 REF

C

0.05 MAX

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.25mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature and may be

located on any of the 4 sides (or ends).

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Compies to JEDEC MO-229 VCED-2.

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