ISL62883CEVAL2Z データシートの表示（PDF） - Intersil
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ISL62883CEVAL2Z Datasheet PDF : 20 Pages
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Application Note 1557
Author: Jia Wei
ISL62883CEVAL2Z User Guide
Introduction
The ISL62883CEVAL2Z evaluation board demonstrates
the performance of the ISL62883 multiphase
synchronous-buck PWM VCORE controller implementing
Intel IMVP-6.5 protocol. The ISL62883 features Intersil's
Robust Ripple Regulator (R3) technology. An on-board
dynamic-load generator is included for evaluating the
transient-load response. It applies a 300µs pulse of
approximately 25mΩ load across VO and PGND.
Contents of this document include:
• Design Criteria
• Recommended Test Equipment
• Interface Connections
• Switch Descriptions
• DIP Switch Descriptions
• Jumper Descriptions
• Test Point Descriptions
• Evaluation Board Documentation
- Bill of materials
- Schematic
- Silk-screen plots
- Board layer plots
TABLE 1. DC/DC DESIGN CRITERIA
PARAMETER
VALUE
UNITS
VIN
VO
Full-load
4.5 to 20
0 to 1.5
75
VDC
VDC
ADC
PWM Frequency
300
kHz
Recommended Equipment
• (QTY 1) Adjustable 25V, 10A Power Supply
• (QTY 1) Fixed 5V, 100mA Power Supply
• (QTY 1) Fixed 12V, 100mA Power Supply
• (QTY 1) Adjustable Constant Current Electronic Load
• (QTY 1) Digital Voltmeter
• (QTY 1) Four-Channel Oscilloscope
Interface Connections
• VIN: Input Voltage to the Power Stage
- J5: VIN Positive Power Input
- TP31: VIN Positive Voltage Sense
- J6: VIN Return Power Input
- TP32: VIN Return Voltage Sense
• VO: Regulated Output Voltage
- J11 and J12: VO Positive Power Output
- J13 and J14: VO Return Power Output
• +5V: +5V Input Voltage
- TP29: +5V Positive Input
- TP30: +5V Return Input
• +12V: Input Voltage for the Dynamic-load Generator
- TP3: 12V Positive Input
- TP2: 12V Return Input
Test Set-up
_
VIN
+
J2
J1
J6
J3
PGND
J5
VIN
ON
S3
OFF
D1
1
S1
0
J4
0 U2 1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
TP37
+3.3V
TP35 TP36
TP29
+
J7
VCCSENSE VSSSENSE PHASE1
J8
PHASE2
J9
+5V
J16 TP30
PHASE3
PGND
5V
_
TP3
TP2
ON
S2
OFF
J10
VCORE
ISL62883CEVAL2Z
J12
VCORE
J14
PGND
J13
PGND
J11
VCORE
FIGURE 1. TEST SET-UP
Switch Descriptions
• S3: Enable
- OFF: Short the VR_ON pin to GND (disable PWM)
- ON: Allow the VR_ON pin to pull-up to +5V (enable
PWM)
• S5: Dynamic Load
- OFF: On-board dynamic load disabled
- ON: On-board dynamic load enabled
April 1, 2010
AN1557.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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