DS21448 データシートの表示（PDF） - Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Maxim Integrated 

Table 4-I. Receive Sensitivity Settings

EGL

(CCR4.4)

0

1

1

0

ETS

(CCR1.7)

0 (E1)

0 (E1)

1 (T1)

1 (T1)

RECEIVE SENSITIVITY

(dB)

-12 (short haul)

-43 (long haul)

-30 (limited long haul)

-36 (long haul)

DS21448 3.3V T1/E1/J1 Quad Line Interface

CCR5 (04H): Common Control Register 5

(MSB)

BPCS1

BPCS0

MM1

MM0

RSCLKE

TSCLKE

RT1

NAME

BPCS1

BPCS0

MM1

MM0

RSCLKE

TSCLKE

RT1

RT0

POSITION

CCR5.7

CCR5.6

CCR5.5

CCR5.4

CCR5.3

CCR5.2

CCR5.1

CCR5.0

FUNCTION

Backplane Clock Frequency Select 1. See Table 4-J for details.

Backplane Clock Frequency Select 0. See Table 4-J for details.

Monitor Mode Gain Select 1 (Table 4-K. )

Monitor Mode Gain Select 0. See (Table 4-K.

Receive Synchronization Clock Enable

0 = disable 2.048MHz synchronization receive mode

1 = enable 2.048MHz synchronization receive mode

Transmit Synchronization Clock Enable

0 = disable 2.048MHz transmit synchronization clock

1 = enable 2.048MHz transmit synchronization clock

Receive Termination Select 1. See Table 4-L for details.

Receive Termination Select 0. See Table 4-L for details.

(LSB)

RT0

Table 4-J. Backplane Clock Select

BPCS1

(CCR5.7)

0

0

1

1

BPCS0

(CCR5.6)

0

1

0

1

BPCLK FREQUENCY (MHz)

16.384

8.192

4.096

2.048

Table 4-K. Monitor Gain Settings

MM1

(CCR5.5)

0

0

1

1

MM0

(CCR5.4)

0

1

0

1

INTERNAL LINEAR GAIN

BOOST (dB)

Normal operation (no boost)

20

26

32

Table 4-L. Internal Rx Termination Select

RT1

(CCR5.1)

0

0

1

1

RT0

(CCR5.0)

0

1

0

1

INTERNAL RECEIVE

TERMINATION CONFIGURATION

Internal receive-side termination disabled

Internal receive-side 120Ω enabled

Internal receive-side 100Ω enabled

Internal receive-side 75Ω enabled

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