MX29LV161DB データシートの表示（PDF） - Macronix International

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MX29LV161DB

16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY

Macronix International 

MX29LV161D T/B

WRITE PULSE "GLITCH" PROTECTION

CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write

cycle.

LOGICAL INHIBIT

A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at

Vih, WE# at Vih, or OE# at Vil.

POWER-UP SEQUENCE

Upon power up, MX29LV161D T/B is placed in read array mode. Furthermore, program or erase operation will

begin only after successful completion of specified command sequences.

POWER-UP WRITE INHIBIT

When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on

the rising edge of WE#.

POWER SUPPLY DECOUPLING

A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.

P/N:PM1359

REV. 1.0, JUN. 03, 2010

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