AAT3236 データシートの表示（PDF） - Advanced Analogic Technologies

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AAT3236

300mA CMOS High Performance LDO

Advanced Analogic Technologies 

AAT3236

300mA CMOS High Performance LDO

tion to ground and the LDO regulator ground con-

nection. When the high load current returns through

this path, a small ripple voltage is created, feeding

into the CBYP loop.

Figure 2 shows the preferred method for the

bypass and output capacitor connections. For low

output noise and highest possible power supply

ripple rejection performance, it is critical to connect

the bypass and output capacitor directly to the LDO

regulator ground pin. This method will eliminate

any load noise or ripple current feedback through

the LDO regulator.

Evaluation Board Layout

The AAT3236 evaluation layout (Figures 3, 4, and

5) follows the recommend printed circuit board lay-

out procedures and can be used as an example for

good application layouts.

Note: Board layout shown is not to scale.

VIN

IIN

DC INPUT

VIN

LDO VOUT

Regulator

EN

BYP

GND

CIN

IRIPPLE

IGND

IBYP + noise

ILOAD

CBYP

GND

LOOP

CBYP

COUT

RLOAD

GND

RTRACE

RTRACE

RTRACE

RTRACE

ILOAD return + noise and ripple

Figure 1: Common LDO Regulator Layout with CBYP Ripple Feedback Loop.

IIN

VIN

DC INPUT

GND

ILOAD

VIN

LDO VOUT

Regulator

EN

BYP

GND

CIN

IRIPPLE

IGND

IBYP only

CBYP

COUT

RTRACE

RTRACE

ILOAD return + noise and ripple

RTRACE

RTRACE

Figure 2: Recommended LDO Regulator Layout.

RLOAD

14

3236.2007.03.1.4

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