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M12L128324A-2M データシートの表示(PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L128324A-2M
ESMT
[Elite Semiconductor Memory Technology Inc. ESMT
M12L128324A-2M Datasheet PDF : 44 Pages
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ESMT
M12L128324A (2M)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A11
RFU
BA0~BA1
RFU
A10/AP
RFU
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0
W.B.L
TM
CAS Latency
BT
Burst Length
Test Mode
A8 A7
Type
A6
0
0 Mode Register Set 0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
0
Write Burst Length
1
A9
Length
1
0
Burst
1
1
Single Bit
1
CAS Latency
Burst Type
Burst Length
A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1
0
0 Reserved 0 Sequential 0
0
0
1
1
0
1
1
1 Interleave 0
0
1
2
2
1
0
2
0
1
0
4
4
1
1
3
0
1
1
8
8
0
0 Reserved
1
0
0 Reserved Reserved
0
1 Reserved
1
0
1 Reserved Reserved
1
0 Reserved
1
1
0 Reserved Reserved
1
1 Reserved
1
1
1 Full Page Reserved
Full Page Length: 256
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2011
Revision: 1.2
8/44

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