HI5766KCAZ データシートの表示（PDF） - Renesas Electronics

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HI5766KCAZ

10-Bit, 60MSPS A/D Converter

Renesas Electronics 

HI5766

Electrical Specifications

ACVL C=C10=pDFV; CTAC1==255o.0CV;,DDifVfeCrCen2t=ial3A.0nVa;loVgRIEnFp+ut=; T2y.5pVic;aVl VRaElFu-es=

2.0V; fS

are Test

= 60 MSPS at 50%

Results at 25oC,

Duty

Cycle;

Unless Otherwise Specified (Continued)

PARAMETER

TIMING CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Aperture Delay, tAP

Aperture Jitter, tAJ

Data Output Hold, tH

Data Output Delay, tOD

Data Output Enable Time, tEN

Data Output Enable Time, tDIS

Data Latency, tLAT

Power-Up Initialization

POWER SUPPLY CHARACTERISTICS

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

-

5

-

ns

-

5

-

psRMS

-

7

-

ns

-

8

-

ns

-

5

-

ns

-

5

-

ns

-

-

7

Cycles

-

-

20

Cycles

Analog Supply Voltage, AVCC

Digital Supply Voltage, DVCC1

Digital Output Supply Voltage, DVCC2

At 3.0V

At 5.0V

4.75

5.0

5.25

V

4.75

5.0

5.25

V

2.7

3.0

3.3

V

4.75

5.0

5.25

V

Supply Current, ICC

VIN+ - VIN- = 1.25V and DFS = “0”

Power Dissipation

VI+ - VIN- = 1.25V and DFS = “0”

Offset Error Sensitivity, VOS

AVCC or DVCC = 5V 5%

Gain Error Sensitivity, FSE

AVCC or DVCC = 5V 5%

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

-

52

-

mA

-

260

-

mW

-

0.4

-

LSB

-

0.8

-

LSB

FN4130 Rev 6.00

March 30, 2005

Page 6 of 16

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