HI5766KCAZ データシートの表示（PDF） - Renesas Electronics
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HI5766KCAZ Datasheet PDF : 16 Pages
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HI5766
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
CODE CENTER
DESCRIPTION
+Full Scale (+FS) -1/4 LSB
+FS - 11/4 LSB
+3/4 LSB
-1/4 LSB
-FS + 13/4 LSB
-Full Scale (-FS) + 3/4 LSB
DIFFERENTIAL
INPUT
VOLTAGE
(VIN+ - VIN-)
0.499756V
0.498779V
732.422V
-244.141V
-0.498291V
-0.499268V
M
LM
L
S
SS
S
B
BB
B
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
11111111110111111111
11111111100111111110
10000000000000000000
01111111111111111111
00000000011000000001
00000000001000000000
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,
(VREF + - VREF-) = 0.5V.
9. VREF+ = 2.5V and VREF- = 2V.
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE input
to logic low for normal operation.
OE INPUT
0
1
DIGITAL DATA OUTPUTS
Active
High Impedance
Supply and Ground Considerations
The HI5766 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The
digital data outputs also have a separate supply pin, DVCC2,
which can be powered from a 3V or 5V supply. This allows the
outputs to interface with 3V logic if so desired.
The part should be mounted on a board that provides separate
low impedance connections for the analog and digital supplies
and grounds. For best performance, the supplies to the HI5766
should be driven by clean, linear regulated supplies. The board
should also have good high frequency decoupling capacitors
mounted as close as possible to the converter. If the part is
powered off a single supply then the analog supply should be
isolated with a ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when using
high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that is
3/4 LSBs below positive Full Scale (+FS) with the offset error
removed. Full Scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the ideal
value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best fit
straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and
the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5766. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the part
is -0.5dB down from Full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers are
quoted in dBc (decibels with respect to carrier) and DO NOT
include any correction factors for normalizing to full scale.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02
FN4130 Rev 6.00
March 30, 2005
Page 14 of 16
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