AAT3190 データシートの表示（PDF） - Advanced Analogic Technologies

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AAT3190

Positive/Negative Charge Pump for Voltage Bias

Advanced Analogic Technologies 

AAT3190

Positive/Negative Charge Pump for Voltage Bias

The voltage rating for the nth flying capacitor in the

negative stage (see Table 2) is:

VFLY(n) = VFWD - VBULK(n)

VIN = 5.0V, VFWD = 0.3V

Stages (n)

VBULK(n)

1

-4.4V

2

-8.8V

3

-13.2V

4

-17.6V

5

-22.0V

6

-26.4V

VFLY(n)

4.7V

9.1V

13.5V

17.9V

22.3V

26.7V

Table 2: Negative Output Capacitor Voltages.

Single Output Operation

If only one of the two channels is needed, it is pos-

sible to disable either output. Connect the respec-

tive FB pin to VIN to disable the output (e.g., con-

nect FBN to VIN in order to disable the negative

output).

Input Capacitors

Input Capacitor

The primary function of the input capacitor is to pro-

vide a low impedance loop for the edges of pulsed

current drawn by the IC. A low ESL X7R or X5R type

ceramic capacitor is ideal for this function. The size

required will vary depending on the load, output volt-

age, and input voltage characteristics. Typically, the

input capacitor should be 5 to 10 times the flying

capacitor. If the source impedance of the input sup-

ply is high, a larger capacitor may be required. To

minimize stray inductance, the capacitor should be

placed as closely as possible to the IC. This keeps

the high frequency content of the input current local-

ized, minimizing radiated and conducted EMI.

Rectifier Diodes

For the rectifiers, use Schottky diodes with a volt-

age rating of 1.5 times the input voltage. The max-

imum steady-state voltage seen by the rectifier

diodes for both the positive and negative charge

pumps (regardless of the number of stages) is:

VREVERSE = VIN - VF

The BAT54S dual Schottky is offered in a SOT23

package that provides a convenient pin-out for the

voltage doubler configuration. The BAT54SDW

quad Schottky in a SOT363 (2x2mm) package is a

good choice for multiple-stage charge pump config-

uration (see Figure 3, Evaluation Board Schematic).

PC Board Layout

The input and reference capacitor should be placed

as close to the IC as possible. Place the program-

ming resistors (R1-R4) close to the IC, minimizing

trace length to FBN and FBP. Figures 4 and 5 display

the evaluation board layout with the TSOPJW-12

package.

12

3190.2006.01.1.2

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