ICS670-04 データシートの表示（PDF） - Integrated Device Technology

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ICS670-04

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER

Integrated Device Technology 

ICS670-04

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER

ZDB AND MULTIPLIER

Parameter

Short Circuit Current

Internal Pull-up Resistor

Input Capacitance

Symbol

Conditions

IOS Each output

RPU OE, select pins

CIN OE, select pins

Min.

Typ.

±50

200

5

Max.

Units

mA

kΩ

pF

AC Electrical Characteristics

VDD = 3.3V ±10%, Ambient Temperature -40 to +85° C, unless stated otherwise

Parameter

Symbol

Conditions

Min. Typ. Max. Units

Input Clock Frequency

Output Clock Frequency

fIN

See table on page 2

5

210 MHz

210 MHz

Output Rise Time

Output Fall Time

Output Clock Duty Cycle

Input to Output Skew

tOR 0.8 to 2.0 V, no load

tOF 2.0 to 0.8 V, no load

tDC measured at VDD/2

Note 1

1.5 ns

1.5 ns

45

50 55

%

±100

ps

Maximum Absolute Jitter

short term

±45

ps

Maximum Jitter

one sigma

15

ps

Phase Noise, relative to

carrier, 125 MHz (x5)

100 Hz offset

1 kHz offset

-103

-117

dBc/Hz

dBc/Hz

10 kHz

-111

dBc/Hz

200 kHz

-88

dBc/Hz

Note 1: Rising edge of ICLK compared with rising edge of CLK2, with FBCLK connected to FBIN, and 15 pF load

on CLK2.

Note for OE1

The OE1 pin is intended to facilitate board test. Note that disabling the FBLK will open the loop, causing a

high-frequency to be output from CLK2. Therefore, set OE1 low only if the chip is in power-down (S3:S0 = 0).

Thermal Characteristics

Parameter

Symbol Conditions

Thermal Resistance Junction to

Ambient

θJA Still air

θJA 1 m/s air flow

θJA 3 m/s air flow

Thermal Resistance Junction to Case θJC

Min.

Typ.

120

115

105

58

Max.

Units

° C/W

° C/W

° C/W

° C/W

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 4

ICS670-04 REV E 051310

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