BLOCK DIAGRAM
SM1125ABV
OSC
SI
SC
ST
OSC
1/2 or 1/4
SW2
Divider
1/128
Control
Circuit
Tempo Latch
Tempo Counter
Rhythm
Counter
Scale
Counter
Scale
ROM
Main
ROM
Multi-
Plexer
Address
Counter
Start
Address
Latch
VSS
VDD
MTO
TEST
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
Name
OSC
SI
SC
ST
TEST
MTO
VDD
VSS
I/O
Function
I
External resistor and capacitor connection pins
I
Playback control serial interface data input
I
Playback control serial interface clock input
I
Playback start/stop control signal input
I
Test input pin. Leave open or tie to VSS. (pull-down resistance built-in)
O
Playback melody signal output
–
Supply pin (+)
–
Ground pin
SEIKO NPC CORPORATION —2