BS62UV256TCP10(2008) データシートの表示（PDF） - Brilliance Semiconductor
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BS62UV256TCP10 Datasheet PDF : 10 Pages
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BS62UV256
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL
=
100pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
ALL INPUT PULSES
90%
10%
→←
Rise Time :
1V/ns
90%
10%
→←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
DESCRIPTION
tAVAX
tRC
Read Cycle Time
tAVQX
tAA
Address Access Time
tE1LQV
tACS
Chip Select Access Time
tGLQV
tOE
Output Enable to Output Valid
tE1LQX
tCLZ
Chip Select to Output Low Z
tGLQX
tOLZ
Output Enable to Output Low Z
tE1HQZ
tCHZ
Chip Select to Output High Z
tGHQZ
tOHZ
Output Enable to Output High Z
tAVQX
tOH
Data Hold from Address Change
CYCLE TIME : 100ns CYCLE TIME : 150ns
MIN. TYP. MAX. MIN. TYP. MAX.
UNITS
100 --
-- 150 --
--
ns
--
-- 100 --
-- 150
ns
--
-- 100 --
-- 150
ns
--
--
50
--
-- 100
ns
10
--
--
10
--
--
ns
10
--
--
10
--
--
ns
--
--
35
--
--
35
ns
--
--
30
--
--
30
ns
10
--
--
10
--
--
ns
R0201-BS62UV256
4
Revision 2.7
Oct.
2008
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